Регистры H616: Cluster 0 Reset Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 29

DDR_RST

Bit 28
R/W
0x1

0: assert
1: de-assert
AXI2MBUS Logic Circuit Reset

Unused

Bits 27 : 26

MBIST_RST

Bit 25
R/W
0x1

CPUBIST Reset
0: assert
1: de-assert
The reset signal is for test

SOC_DBG_RST

Bit 24
R/W
0x1

Cluster SOC Debug Reset
0: assert
1: de-assert

ETM_RST

Bits 23 : 20
R/W
0xF

Cluster ETM Reset Assert
0: assert
1: de-assert

DBG_RST

Bits 19 : 16
R/W
0xF

Cluster Debug Reset Assert
0: assert
1: de-assert

Unused

Bits 15 : 9

L2_RST

Bit 8
R/W
0x1

Cluster L2 Cache Reset
0: assert
1: de-assert

Unused

Bits 7 : 4

CORE_RESET

Bits 3 : 0
R/W
0x1

Cluster CPU[3:0] Reset Assert
0: assert
1: de-assert

Bit fields structure

typedef union c0_rst_ctrl { struct { unsigned core_reset : 4; unsigned unused0 : 4; unsigned l2_rst : 1; unsigned unused1 : 7; unsigned dbg_rst : 4; unsigned etm_rst : 4; unsigned soc_dbg_rst : 1; unsigned mbist_rst : 1; unsigned unused2 : 2; unsigned ddr_rst : 1; unsigned unused3 : 3; } b; unsigned long w; } C0_RST_CTRL