C0_CTRL_REG0 Конфигурация CPUX: список регистров 31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16 15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00 SYSBAR_DISABLE Bit 31R/W 0x1 Disable broadcasting of barriers onto system bus BROADCAST_INNER Bit 30R/W 0x0 Enable broadcasting of inner shareable transactions BROADCAST_OUTER Bit 29R/W 0x0 Enable broadcasting of outer shareable transactions BROADCAST_CACHE_MAINT Bit 28R/W 0x0 0: Cache maintenance operations are not broadcasted to downstream caches AA_64_NAA_32 Bits 27 : 24R/W 0x0 0: AArch32 Unused Bits 23 : 12CP15S_DISABLE Bits 11 : 8R/W 0x0 Disable write access to some secure CP15 register. Unused Bits 7 : 5L2_RST_DISABLE Bit 4R/W 0x0 Disable automatic L2 cache invalidate at reset L1_RST_DISABLE. Bits 3 : 0R/W 0x0 Disable automatic Cluster CPU[3:0] L1 cache invalidate at reset: Команда U-Boot для чтения регистра md 9010010 1md 8100010 1 Bit fields structuretypedef union c0_ctrl_reg0 { struct { unsigned l1_rst_disable. : 4; unsigned l2_rst_disable : 1; unsigned unused0 : 3; unsigned cp15s_disable : 4; unsigned unused1 : 12; unsigned aa_64_naa_32 : 4; unsigned broadcast_cache_maint : 1; unsigned broadcast_outer : 1; unsigned broadcast_inner : 1; unsigned sysbar_disable : 1; } b; unsigned long w; } C0_CTRL_REG0 |