Регистры H616: GIC and Jtag Reset Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 20

EXM_CLR_3_0

Bits 19 : 16
R/W
0x0

Clear the status of interface, for debug

Unused

Bits 15 : 12

CS_RST

Bit 11
R/W
0x1

CoreSight Reset
0: assert
1: de-assert

DAP_RST

Bit 10
R/W
0x1

DAP Reset
0: assert
1: de-assert

PORTRST

Bit 9
R/W
0x1

Jtag portrst
0: assert
1: de-assert

TRST

Bit 8
R/W
0x1

Jtag trst
0: assert
1: de-assert

Unused

Bits 7 : 2

IDC_RST

Bit 1
R/W
0x1

Interrupt delay controller reset
0: assert
1: de-assert

GIC_RST

Bit 0
R/W
0x1

GIC_reset_cpu_reg
0: assert
1: de-assert

Bit fields structure

typedef union gic_jtag_rst_ctrl { struct { unsigned gic_rst : 1; unsigned idc_rst : 1; unsigned unused0 : 6; unsigned trst : 1; unsigned portrst : 1; unsigned dap_rst : 1; unsigned cs_rst : 1; unsigned unused1 : 4; unsigned exm_clr_3_0 : 4; unsigned unused2 : 12; } b; unsigned long w; } GIC_JTAG_RST_CTRL