Регистры H616: EMAC-EPHY Clock Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

EMAC0_BPS_EFFUSE

Bits 31 : 28
R/W
0x0

EMAC0_XMII_SEL

Bit 27
R/W
0x0

0: Internal SMI and MII
1: External SMI and MII

EMAC0_EPHY_MODE

Bits 26 : 25
R/W
0x0

Operation Mode Selection
00 : Normal Mode
01 : Sim Mode
10 : AFE Test Mode
11:/

EMAC0_PHY_ADDR

Bits 24 : 20
R/W
0x0

PHY Address

Unused

Bit 19

EMAC0_CLK_SEL

Bit 18
R/W
0x1

0: 25 MHz
1: 24 MHz

EMAC0_LED_POL

Bit 17
R/W
0x0

0: High active
1: Low active

EMAC0_SHUTDOWN

Bit 16
R/W
0x1

0: Power up
1: Shutdown

EMAC0_PHY_SELECT

Bit 15
R/W
0x1

0: External PHY
1: Internal PHY

Unused

Bit 14

EMAC0_RMII_EN

Bit 13
R/W
0x0

0: Disable RMII Module
1: Enable RMII Module
When this bit is asserted, MII or RGMII interface is disabled (This means bit13 is prior to bit2)

EMAC0_ETXDC

Bits 12 : 10
R/W
0x0

Configure EMAC Transmit Clock Delay Chain

EMAC0_ERXDC

Bits 9 : 5
R/W
0x0

Configure EMAC Receive Clock Delay Chain

EMAC0_ERXIE

Bit 4
R/W
0x0

Enable EMAC Receive Clock Invertor
0: Disable
1: Enable

EMAC0_ETXIE

Bit 3
R/W
0x0

Enable EMAC Transmit Clock Invertor
0: Disable
1: Enable

EMAC0_EPIT

Bit 2
R/W
0x0

EMAC PHY Interface Type
0: MII
1: RGMII

EMAC0_ETCS

Bits 1 : 0
R/W
0x0

EMAC Transmit Clock Source
00: Transmit clock source for MII
01: External transmit clock source for GMII and RGMII
10: Internal transmit clock source for GMII and RGMII
11: Reserved

Note
When configuring RMII interface, the bit13 should be written to 1, and the bit2 should be written to 0. Select TXCLK as the clock source of RMII, the bit0 can be written to 0.

Bit fields structure

typedef union emac_ephy_clk_reg0 { struct { unsigned emac0_etcs : 2; unsigned emac0_epit : 1; unsigned emac0_etxie : 1; unsigned emac0_erxie : 1; unsigned emac0_erxdc : 5; unsigned emac0_etxdc : 3; unsigned emac0_rmii_en : 1; unsigned unused0 : 1; unsigned emac0_phy_select : 1; unsigned emac0_shutdown : 1; unsigned emac0_led_pol : 1; unsigned emac0_clk_sel : 1; unsigned unused1 : 1; unsigned emac0_phy_addr : 5; unsigned emac0_ephy_mode : 2; unsigned emac0_xmii_sel : 1; unsigned emac0_bps_effuse : 4; } b; unsigned long w; } EMAC_EPHY_CLK_REG0