Unused Bits 31 : 8
TMR1_MODE Bit 7
R/W
0x0
Timer 1 mode
0: Continuous mode. When interval value reached, the timer will not disable
automatically.
1: Single mode. When interval value reached, the timer will disable
automatically.
TMR1_CLK_PRES Bits 6 : 4
R/W
0x0
Select the pre-scale of timer 1 clock source
000: /1
001: /2
010: /4
011: /8
100: /16
101: /32
110: /64
111: /128
TMR1_CLK_SRC Bits 3 : 2
R/W
0x1
00: LOSC
01: OSC24M
10: /
11: /
TMR1_RELOAD Bit 1
R/W
0x0
Timer 1 Reload
0: No effect
1: Reload timer 1 Interval value
After the bit is set, it can not be written again before it is cleared automatically.
TMR1_EN Bit 0
R/W
0x0
Timer 1 Enable
0: Stop/Pause
1: Start
If the timer starts, it will reload the interval value to internal register, and the
current counter will count from interval value to 0.
If the current counter does not reach the zero, the timer enable bit is set to 0 , the current value counter will pause. At least wait for 2 cycles, the start bit can be set to 1.
In timer pause state, the interval value register can be modified. If the timer starts again, and the software hopes the current value register to down-count from the new interval value, the reload bit and the enable bit should be set to 1 at the same time.
Команда U-Boot для чтения регистра md 3009020 1
Bit fields structure
typedef union tmr1_ctrl_reg
{
struct
{
unsigned tmr1_en : 1;
unsigned tmr1_reload : 1;
unsigned tmr1_clk_src : 2;
unsigned tmr1_clk_pres : 3;
unsigned tmr1_mode : 1;
unsigned unused0 : 24;
} b;
unsigned long w;
} TMR1_CTRL_REG
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