HS_TMR0_TEST Bit 31
R/W
0x0
High Speed Timer 0 Test Mode
In test mode, the low register should be set to 0x1, the high register will
down counter. The counter needs to be reloaded.
0: Normal mode
1: Test mode
Unused Bits 30 : 8
HS_TMR0_MODE Bit 7
R/W
0x0
High Speed Timer 0 Mode
0: Continuous mode. When interval value reached, the timer will not disable
automatically.
1: Single mode. When interval value reached, the timer will disable
automatically.
HS_TMR0_CLK Bits 6 : 4
R/W
0x0
Select the pre-scale of the high speed timer 0 clock sources.
000: /1
001: /2
010: /4
011: /8
100: /16
101: /
110: /
111: /
Unused Bits 3 : 2
HS_TMR0_RELOAD Bit 1
R/W1S
0x0
High Speed Timer 0 Reload
0: No effect
1: Reload High Speed Timer 0 Interval Value
HS_TMR0_EN Bit 0
R/W
0x0
High Speed Timer 0 Enable
0: Stop/Pause
1: Start
If the timer starts, it will reload the interval value to internal register, and the
current counter will count from interval value to 0.
If the current counter does not reach the zero, the timer enable bit is set to
0 , the current value counter will pause. At least wait for 2 cycles, the start
bit can be set to 1.
In timer pause state, the interval value register can be modified. If the timer
starts again, and the software hopes the current value register to down-count
from the new interval value, the reload bit and the enable bit should be set
to 1 at the same time.
Команда U-Boot для чтения регистра md 3005020 1
Bit fields structure
typedef union hs_tmr0_ctrl_reg
{
struct
{
unsigned hs_tmr0_en : 1;
unsigned hs_tmr0_reload : 1;
unsigned unused0 : 2;
unsigned hs_tmr0_clk : 3;
unsigned hs_tmr0_mode : 1;
unsigned unused1 : 23;
unsigned hs_tmr0_test : 1;
} b;
unsigned long w;
} HS_TMR0_CTRL_REG
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