Регистры Allwinner H616
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DMA_IRQ_PEND_REG0
3.9.5. DMA IRQ Pending Register 0 - адрес: 0x3002010 (смещение: 0x0010)

Прямой доступ к памяти: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

  Unused

Bit 31

  DMA7_QUEUE_IRQ_PEND

Bit 30
R/W1C
0x0

DMA 7 Queue End Transfer Interrupt Pending. Setting 1 to the bit will
clear it.
0: No effect
1: Pending

  DMA7_PKG_IRQ_PEND

Bit 29
R/W1C
0x0

DMA 7 Package End Transfer Interrupt Pending. Setting 1 to the bit will
clear it.
0: No effect
1: Pending

  DMA7_HLAF_IRQ_PEND

Bit 28
R/W1C
0x0

DMA 7 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it
0: No effect
1: Pending

  Unused

Bit 27

  DMA6_QUEUE_IRQ_PEND

Bit 26
R/W1C
0x0

DMA 6 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it

0: No effect
1: Pending

  DMA6_PKG_IRQ_PEND

Bit 25
R/W1C
0x0

DMA 6 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it

0: No effect
1: Pending

  DMA6_HLAF_IRQ_PEND

Bit 24
R/W1C
0x0

DMA 6 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it

0: No effect
1: Pending

  Unused

Bit 23

  DMA5_QUEUE_IRQ_PEND

Bit 22
R/W1C
0x0

DMA 5 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it

0: No effect
1: Pending

  DMA5_PKG_IRQ_PEND

Bit 21
R/W1C
0x0

DMA 5 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it

0: No effect
1: Pending

  DMA5_HLAF_IRQ_PEND

Bit 20
R/W1C
0x0

DMA 5 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it


0: No effect
1: Pending

  Unused

Bit 19

  DMA4_QUEUE_IRQ_PEND

Bit 18
R/W1C
0x0

DMA 4 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it

0: No effect
1: Pending

  DMA4_PKG_IRQ_PEND

Bit 17
R/W1C
0x0

DMA 4 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA4_HLAF_IRQ_PEND

Bit 16
R/W1C
0x0

DMA 4 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  Unused

Bit 15

  DMA3_QUEUE_IRQ_PEND

Bit 14
R/W1C
0x0

DMA 3 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending.

  DMA3_PKG_IRQ_PEND

Bit 13
R/W1C
0x0

DMA 3 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA3_HLAF_IRQ_PEND

Bit 12
R/W1C
0x0

DMA 3 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  Unused

Bit 11

  DMA2_QUEUE_IRQ_PEND

Bit 10
R/W1C
0x0

DMA 2 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA2_PKG_IRQ_PEND

Bit 9
R/W1C
0x0

DMA 2 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA2_HLAF_IRQ_PEND

Bit 8
R/W1C
0x0

DMA 2 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  Unused

Bit 7

  DMA1_QUEUE_IRQ_PEND

Bit 6
R/W1C
0x0

DMA 1 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.
0: No effect
1: Pending

  DMA1_PKG_IRQ_PEND

Bit 5
R/W1C
0x0

DMA 1 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA1_HLAF_IRQ_PEND

Bit 4
R/W1C
0x0

DMA 1 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  Unused

Bit 3

  DMA0_QUEUE_IRQ_PEND

Bit 2
R/W1C
0x0

DMA 0 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA0_PKG_IRQ_PEND

Bit 1
R/W1C
0x0

DMA 0 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA0_HLAF_IRQ_PEND

Bit 0
R/W1C
0x0

DMA 0 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

Команда U-Boot для чтения регистра

md 3002010 1

Bit fields structure 

typedef union  dma_irq_pend_reg0
{
  struct
  {
   unsigned dma0_hlaf_irq_pend : 1;
   unsigned dma0_pkg_irq_pend : 1;
   unsigned dma0_queue_irq_pend : 1;
   unsigned unused0 : 1;
   unsigned dma1_hlaf_irq_pend : 1;
   unsigned dma1_pkg_irq_pend : 1;
   unsigned dma1_queue_irq_pend : 1;
   unsigned unused1 : 1;
   unsigned dma2_hlaf_irq_pend : 1;
   unsigned dma2_pkg_irq_pend : 1;
   unsigned dma2_queue_irq_pend : 1;
   unsigned unused2 : 1;
   unsigned dma3_hlaf_irq_pend : 1;
   unsigned dma3_pkg_irq_pend : 1;
   unsigned dma3_queue_irq_pend : 1;
   unsigned unused3 : 1;
   unsigned dma4_hlaf_irq_pend : 1;
   unsigned dma4_pkg_irq_pend : 1;
   unsigned dma4_queue_irq_pend : 1;
   unsigned unused4 : 1;
   unsigned dma5_hlaf_irq_pend : 1;
   unsigned dma5_pkg_irq_pend : 1;
   unsigned dma5_queue_irq_pend : 1;
   unsigned unused5 : 1;
   unsigned dma6_hlaf_irq_pend : 1;
   unsigned dma6_pkg_irq_pend : 1;
   unsigned dma6_queue_irq_pend : 1;
   unsigned unused6 : 1;
   unsigned dma7_hlaf_irq_pend : 1;
   unsigned dma7_pkg_irq_pend : 1;
   unsigned dma7_queue_irq_pend : 1;
   unsigned unused7 : 1;
  } b;
   unsigned long w;
} DMA_IRQ_PEND_REG0
Allwinner H616 Manual