Регистры Allwinner H616
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DMA_IRQ_PEND_REG1
3.9.5. DMA IRQ Pending Register 1 - адрес: 0x3002014 (смещение: 0x0014)

Прямой доступ к памяти: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

  Unused

Bit 31

  DMA15_QUEUE_IRQ_PEND

Bit 30
R/W1C
0x0

DMA 15 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA15_PKG_IRQ_PEND

Bit 29
R/W1C
0x0

DMA 15 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA15_HLAF_IRQ_PEND

Bit 28
R/W1C
0x0

DMA 15 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  Unused

Bit 27

  DMA14_QUEUE_IRQ_PEND

Bit 26
R/W1C
0x0

DMA 14 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA14_PKG_IRQ_PEND

Bit 25
R/W1C
0x0

DMA 14 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA14_HLAF_IRQ_PEND

Bit 24
R/W1C
0x0

DMA 14 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  Unused

Bit 23

  DMA13_QUEUE_IRQ_PEND

Bit 22
R/W1C
0x0

DMA 13 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA13_PKG_IRQ_PEND

Bit 21
R/W1C
0x0

DMA 13 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA13_HLAF_IRQ_PEND

Bit 20
R/W1C
0x0

DMA 13 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  Unused

Bit 19

  DMA12_QUEUE_IRQ_PEND

Bit 18
R/W1C
0x0

DMA 12 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA12_PKG_IRQ_PEND

Bit 17
R/W1C
0x0

DMA 12 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA12_HLAF_IRQ_PEND

Bit 16
R/W1C
0x0

DMA 12 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.
0: No effect
1: Pending0x0

  Unused

Bit 15

  DMA11_QUEUE_IRQ_PEND

Bit 14
R/W1C
0x0

DMA 11 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending.

  DMA11_PKG_IRQ_PEND

Bit 13
R/W1C
0x0

DMA 11 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA11_HLAF_IRQ_PEND

Bit 12
R/W1C
0x0

DMA 11 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  Unused

Bit 11

  DMA10_QUEUE_IRQ_PEND

Bit 10
R/W1C
0x0

DMA 10 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA10_PKG_IRQ_PEND

Bit 9
R/W1C
0x0

DMA 10 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA10_HLAF_IRQ_PEND

Bit 8
R/W1C
0x0

DMA 10 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  Unused

Bit 7

  DMA9_QUEUE_IRQ_PEND

Bit 6
R/W1C
0x0

DMA 9 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA9_PKG_IRQ_PEND

Bit 5
R/W1C
0x0

DMA 9 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA9_HLAF_IRQ_PEND

Bit 4
R/W1C
0x0

DMA 9 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  Unused

Bit 3

  DMA8_QUEUE_IRQ_PEND

Bit 2
R/W1C
0x0

DMA 8 Queue End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA8_PKG_IRQ_PEND

Bit 1
R/W1C
0x0

DMA 8 Package End Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

  DMA8_HLAF_IRQ_PEND

Bit 0
R/W1C
0x0

DMA 8 Half Package Transfer Interrupt Pending. Setting 1 to the bit will clear it.

0: No effect
1: Pending

Команда U-Boot для чтения регистра

md 3002014 1

Bit fields structure 

typedef union  dma_irq_pend_reg1
{
  struct
  {
   unsigned dma8_hlaf_irq_pend : 1;
   unsigned dma8_pkg_irq_pend : 1;
   unsigned dma8_queue_irq_pend : 1;
   unsigned unused0 : 1;
   unsigned dma9_hlaf_irq_pend : 1;
   unsigned dma9_pkg_irq_pend : 1;
   unsigned dma9_queue_irq_pend : 1;
   unsigned unused1 : 1;
   unsigned dma10_hlaf_irq_pend : 1;
   unsigned dma10_pkg_irq_pend : 1;
   unsigned dma10_queue_irq_pend : 1;
   unsigned unused2 : 1;
   unsigned dma11_hlaf_irq_pend : 1;
   unsigned dma11_pkg_irq_pend : 1;
   unsigned dma11_queue_irq_pend : 1;
   unsigned unused3 : 1;
   unsigned dma12_hlaf_irq_pend : 1;
   unsigned dma12_pkg_irq_pend : 1;
   unsigned dma12_queue_irq_pend : 1;
   unsigned unused4 : 1;
   unsigned dma13_hlaf_irq_pend : 1;
   unsigned dma13_pkg_irq_pend : 1;
   unsigned dma13_queue_irq_pend : 1;
   unsigned unused5 : 1;
   unsigned dma14_hlaf_irq_pend : 1;
   unsigned dma14_pkg_irq_pend : 1;
   unsigned dma14_queue_irq_pend : 1;
   unsigned unused6 : 1;
   unsigned dma15_hlaf_irq_pend : 1;
   unsigned dma15_pkg_irq_pend : 1;
   unsigned dma15_queue_irq_pend : 1;
   unsigned unused7 : 1;
  } b;
   unsigned long w;
} DMA_IRQ_PEND_REG1
Allwinner H616 Manual