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NDFC_CTL
5.2.5. NDFC Configure and Control Register - адрес: 0x4011000 (смещение: 0x0000)

Контроллер Nand Flash (NDFC): список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

  Unused

Bits 31 : 29

  NDFC_DDR_TYPE

Bit 28
R/W
0x0

Type of DDR data interface
This bit is valid when NF_TYPE is 0x2 or 0x3.
0: DDR
1: DDR2

  NDFC_CE_SEL

Bits 27 : 24
R/W
0x0

Chip Select for NAND Flash Chips
0000: NDFC Select Chip 0
0001: NDFC Select Chip 1
0010: NDFC Select Chip 2
0011: NDFC Select Chip 3
0100: NDFC Select Chip 4
0101: NDFC Select Chip 5
0110: NDFC Select Chip 6
0111: NDFC Select Chip 7
1000: NDFC Select Chip 8
1001: NDFC Select Chip 9
1010: NDFC Select Chip 10
1011: NDFC Select Chip 11
1100: NDFC Select Chip 12
1101: NDFC Select Chip 13
1110: NDFC Select Chip 14
1111: NDFC Select Chip 15

  Unused

Bits 23 : 22

  NDFC_DDR_RM

Bit 21
R/W
0x0

DDR Repeat Data Mode
0: Lower byte
1: Higher byte

  NDFC_DDR_REN

Bit 20
R/W
0x0

DDR Repeat Enable
0: Disable
1: Enable

  NF_TYPE

Bits 19 : 18
R/W
0x0

NAND Flash Type
00: Normal SDR NAND
01: Reserved
10: ONFI DDR NAND
11: Toggle DDR NAND

  NDFC_CLE_POL

Bit 17
R/W
0x0

NDFC Command Latch Enable (CLE) Signal Polarity Select
0: High active
1: Low active

  NDFC_ALE_POL

Bit 16
R/W
0x0

NDFC Address Latch Enable (ALE) Signal Polarity Select
0: High active
1: Low active

  NDFC_DMA_TYPE

Bit 15
R/W
0x0

0: Dedicated DMA
1: Normal DMA

  NDFC_RAM_METHOD

Bit 14
R/W
0x0

Access internal RAM method
0: Access internal RAM by AHB method
1: Access internal RAM by DMA method

  Unused

Bits 13 : 12

  NDFC_PAGE_SIZE

Bits 11 : 8
R/W
0x0

000: 1KB
001: 2KB
010: 4KB
011: 8KB
100: 16KB
101: 32KB
The page size is for main field data.

  Unused

Bit 7

  NDFC_CE_ACT

Bit 6
R/W
0x0

Chip Select Signal CE# Control during NAND Operation
0: De-active Chip Select Signal NDFC_CE# during data loading, serial access and
other no operation stage for power consumption. NDFC automatic controls Chip
Select Signals.
1: Chip select signal NDFC_CE# is always active after NDFC is enabled

  Unused

Bit 5

  NDFC_RB_SEL

Bits 4 : 3
R/W
0x0

NDFC External R/B Signal Select
The value 0-3 selects the external R/B signal. The same R/B signal can be used
for multiple chip select flash.

  NDFC_BUS_WIDTH

Bit 2
R/W
0x0

0: 8-bit bus
1: 16-bit bus

  NDFC_RESET

Bit 1
R/W1C
0x0

NDFC Reset
Write 1 to reset NDFC and clear to 0 after reset

  NDFC_EN

Bit 0
R/W
0x0

NDFC Enable Control
0: Disable NDFC
1: Enable NDFC

Команда U-Boot для чтения регистра

md 4011000 1

Bit fields structure 

typedef union  ndfc_ctl
{
  struct
  {
   unsigned ndfc_en : 1;
   unsigned ndfc_reset : 1;
   unsigned ndfc_bus_width : 1;
   unsigned ndfc_rb_sel : 2;
   unsigned unused0 : 1;
   unsigned ndfc_ce_act : 1;
   unsigned unused1 : 1;
   unsigned ndfc_page_size : 4;
   unsigned unused2 : 2;
   unsigned ndfc_ram_method : 1;
   unsigned ndfc_dma_type : 1;
   unsigned ndfc_ale_pol : 1;
   unsigned ndfc_cle_pol : 1;
   unsigned nf_type : 2;
   unsigned ndfc_ddr_ren : 1;
   unsigned ndfc_ddr_rm : 1;
   unsigned unused3 : 2;
   unsigned ndfc_ce_sel : 4;
   unsigned ndfc_ddr_type : 1;
   unsigned unused4 : 3;
  } b;
   unsigned long w;
} NDFC_CTL
Allwinner H616 Manual