Регистры Allwinner H616

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NDFC_ST
5.2.5. NDFC Status Information Register - адрес: 0x4011004 (смещение: 0x0004)

Контроллер Nand Flash (NDFC): список регистров



31 ||||||||||||||||| 16
15 ||||||||||||||||| 00

  Unused

Bits 31 : 14

  NDFC_RDATA_STA_0

Bit 13
R
0x0

0: The number of bit 1 during current read operation is more than threshold
value.
1: The number of bit 1 during current read operation is less than or equal to
threshold value.
This field only is valid when NDFC_RDATA_STA_EN is 1.
The threshold value is configured in NDFC_RDATA_STA_TH.


  NDFC_RDATA_STA_1

Bit 12
R
0x0

0: The number of bit 0 during current read operation is more than threshold value.
1: The number of bit 0 during current read operation is less than or equal to the
threshold value.
This field only is valid when NDFC_RDATA_STA_EN is 1.
The threshold value is configured in NDFC_RDATA_STA_TH.


  NDFC_RB_STATE3

Bit 11
R
0x1

NAND Flash R/B 3 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State


  NDFC_RB_STATE2

Bit 10
R
0x1

NAND Flash R/B 2 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State


  NDFC_RB_STATE1

Bit 9
R
0x1

NAND Flash R/B 1 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State


  NDFC_RB_STATE0

Bit 8
R
0x1

NAND Flash R/B 0 Line State
0: NAND Flash in BUSY State
1: NAND Flash in READY State


  Unused

Bits 7 : 5

  NDFC_STA

Bit 4
R
0x0

0: NDFC FSM in IDLE state
1: NDFC FSM in BUSY state
When NDFC_STA is 0, NDFC can accept new command and process command.


  NDFC_CMD_FIFO_STATUS

Bit 3
R
0x0

0: Command FIFO not full and can receive new command
1: Full and waiting NDFC to process commands in FIFO
Since there is only one 32-bit FIFO for command. When NDFC latches one
command, command FIFO is free and can accept another new command.


  NDFC_DMA_INT_FLAG

Bit 2
R/W1C
0x0

When it is 1, it means that a pending DMA is completed. It will be cleared after
writing 1 to this bit or it will be automatically cleared before FSM processing an
new command.


  NDFC_CMD_INT_FLAG

Bit 1
R/W1C
0x0

When it is 1, it means that NDFC has finished one Normal Command Mode or
one Batch Command Work Mode. It will be cleared after writing 1 to this bit or
it will be automatically cleared before FSM processing an new command.


  NDFC_RB_B2R

Bit 0
R/W1C
0x0

When it is 1, it means that NDFC_R/B# signal is transferred from BUSY state to
READY state. It will be cleared after writing 1 to this bit.



Команда U-Boot для чтения регистра

md 4011004 1



Bit fields structure

typedef union  ndfc_st
{
  struct
  {
   unsigned ndfc_rb_b2r : 1;
   unsigned ndfc_cmd_int_flag : 1;
   unsigned ndfc_dma_int_flag : 1;
   unsigned ndfc_cmd_fifo_status : 1;
   unsigned ndfc_sta : 1;
   unsigned unused0 : 3;
   unsigned ndfc_rb_state0 : 1;
   unsigned ndfc_rb_state1 : 1;
   unsigned ndfc_rb_state2 : 1;
   unsigned ndfc_rb_state3 : 1;
   unsigned ndfc_rdata_sta_1 : 1;
   unsigned ndfc_rdata_sta_0 : 1;
   unsigned unused1 : 18;
  } b;
   unsigned long w;
} NDFC_ST
   

Allwinner H616 Manual