Регистры H616: NDFC Interrupt Control Register

NDFC_INT

5.2.5. NDFC Interrupt Control Register - адрес: 0x4011008 (смещение: 0x0008)

Контроллер Nand Flash (NDFC): список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 3

NDFC_DMA_INT_ENABLE

Bit 2
R/W
0x0

Enable or disable interrupt when a pending DMA is completed.

NDFC_CMD_INT_ENABLE

Bit 1
R/W
0x0

Enable or disable interrupt when NDFC has finished the procession of a single
command in normal command work mode or one batch command work mode.
0: Disable
1: Enable

NDFC_B2R_INT_ENABLE

Bit 0
R/W
0x0

Enable or disable interrupt when NDFC_RB# signal is transferring from BUSY state to READY state

0: Disable
1: Enable

Bit fields structure

typedef union ndfc_int { struct { unsigned ndfc_b2r_int_enable : 1; unsigned ndfc_cmd_int_enable : 1; unsigned ndfc_dma_int_enable : 1; unsigned unused0 : 29; } b; unsigned long w; } NDFC_INT