Регистры H616: NDFC Timing Control Register

NDFC_TIMING_CTL

5.2.5. NDFC Timing Control Register - адрес: 0x401100c (смещение: 0x000C)

Контроллер Nand Flash (NDFC): список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 12

NDFC_READ_PIPE

Bits 11 : 8
R/W
0x0

In SDR mode:
00: Normal
01: EDO
10: E-EDO
Others: Reserved
In DDR mode:
1~15 is valid.(These bits configure the number of clock when data is valid after
RE#'s falling edge)

Unused

Bits 7 : 6

NDFC_DC_CTL

Bits 5 : 0
R/W
0x0

NDFC Delay Chain Control.
These bits are only valid in DDR data interface, and configure the relative phase
between DQS and DQ[0...7] .

Bit fields structure

typedef union ndfc_timing_ctl { struct { unsigned ndfc_dc_ctl : 6; unsigned unused0 : 2; unsigned ndfc_read_pipe : 4; unsigned unused1 : 20; } b; unsigned long w; } NDFC_TIMING_CTL