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NDFC_TIMING_CFG
5.2.5. NDFC Timing Configure Register - адрес: 0x4011010 (смещение: 0x0010)

Контроллер Nand Flash (NDFC): список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

  Unused

Bits 31 : 20

  T_WC

Bits 19 : 18
R/W
0x0

Write Cycle Time
00: 1*2T
01: 2*2T
10: 3*2T
11: 4*2T

  T_CCS

Bits 17 : 16
R/W
0x0

Change Column Setup Time
00: 12*2T
01: 20*2T
10: 28*2T
11: 60*2T

  T_CLHZ

Bits 15 : 14
R/W
0x0

CLE High to Output Hi-z
00: 2*2T
01: 8*2T
10: 16*2T
11: 31*2T

  T_CS

Bits 13 : 12
R/W
0x0

CE Setup Time
00: 2*2T
01: 8*2T
10: 16*2T
11: 31*2T

  T_CDQSS

Bit 11
R/W
0x0

DQS Setup Time for Data Input Start
0: 4*2T
1: 20*2T

  T_CAD

Bits 10 : 8
R/W
0x0

Command, Address, Data Delay
000: 2*2T
001: 6*2T
010: 10*2T
011: 14*2T
100: 22*2T
101: 30*2T
110/111: 62*2T

  T_RHW

Bits 7 : 6
R/W
0x2

Cycle Number from RE# High to WE# Low
00: 4*2T
01: 12*2T
10: 20*2T
11: 28*2T

  T_WHR

Bits 5 : 4
R/W
0x1

Cycle Number from WE# High to RE# Low
00: 0*2T
01: 6*2T
10: 14*2T
11: 22*2T

  T_ADL

Bits 3 : 2
R/W
0x1

Cycle Number from Address to Data Loading
00: 0*2T
01: 6*2T
10: 14*2T
11: 22*2T

  T_WB

Bits 1 : 0
R/W
0x1

Cycle Number from WE# High to Busy
00:14*2T
01: 22*2T
10: 30*2T
11: 38*2T

Команда U-Boot для чтения регистра

md 4011010 1

Bit fields structure 

typedef union  ndfc_timing_cfg
{
  struct
  {
   unsigned t_wb : 2;
   unsigned t_adl : 2;
   unsigned t_whr : 2;
   unsigned t_rhw : 2;
   unsigned t_cad : 3;
   unsigned t_cdqss : 1;
   unsigned t_cs : 2;
   unsigned t_clhz : 2;
   unsigned t_ccs : 2;
   unsigned t_wc : 2;
   unsigned unused0 : 12;
  } b;
   unsigned long w;
} NDFC_TIMING_CFG
Allwinner H616 Manual