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IOMMU_RESET_REG
3.12.5. IOMMU ResetRegister - адрес: 0x30f0010 (смещение: 0x0010)

Модуль управления памятью ввода-вывода IOMMU: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

  IOMMU_RESET

Bit 31
R/W
0x1

IOMMU Software Reset Switch
0: Set reset signal
1: Release reset signal
Before IOMMU software reset operation, ensure IOMMU never be
opened; Or all bus operations are completed; Or DRAM and the
peripherals have opened the corresponding switch, for shielding the
effects of IOMMU reset.

  Unused

Bits 30 : 18

  PTW_CACHE_RESET

Bit 17
R/W
0x1

PTW Cache address convert lane software reset switch.
0: Set reset signal
1: Release reset signal
When PTW Cache occurs abnormal, the bit is used to reset PTW Cache
individually.

  MACRO_TLB_RESET

Bit 16
R/W
0x1

Macro TLB address convert lane software reset switch.
0: Set reset signal
1: Release reset signal
When PTW Cache occurs abnormal, the bit is used to reset PTW Cache
individually.

  Unused

Bits 15 : 7

  MASTER6_RESET

Bit 6
R/W
0x1

Master6 address convert lane software reset switch.
0: Set reset signal
1: Release reset signal
When Master6 occurs abnormal, the bit is used to reset PTW Cache
individually.

  MASTER5_RESET

Bit 5
R/W
0x1

Master5 address convert lane software reset switch.
0: Set reset signal
1: Release reset signal
When Master5 occurs abnormal, the bit is used to reset PTW Cache
individually.

  MASTER4_RESET

Bit 4
R/W
0x1

Master4 address convert lane software reset switch.
0: Set reset signal
1: Release reset signal
When Master4 occurs abnormal, the bit is used to reset PTW Cache
individually.

  MASTER3_RESET

Bit 3
R/W
0x1

Master3 address convert lane software reset switch.
0: Set reset signal
1: Release reset signal
When Master3 occurs abnormal, the bit is used to reset PTW Cache
individually.

  MASTER2_RESET

Bit 2
R/W
0x1

Master2 address convert lane software reset switch.
0: Set reset signal
1: Release reset signal
When Master2 occurs abnormal, the bit is used to reset PTW Cache
individually.

  MASTER1_RESET

Bit 1
R/W
0x1

Master1 address convert lane software reset switch.
0: Set reset signal
1: Release reset signal
When Master1 occurs abnormal, the bit is used to reset PTW Cache
individually.

  MASTER0_RESET

Bit 0
R/W
0x1

Master0 address convert lane software reset switch.
0: Set reset signal
1: Release reset signal
When Master0 occurs abnormal, the bit is used to reset PTW Cache individually.

Команда U-Boot для чтения регистра

md 30f0010 1

Bit fields structure 

typedef union  iommu_reset_reg
{
  struct
  {
   unsigned master0_reset : 1;
   unsigned master1_reset : 1;
   unsigned master2_reset : 1;
   unsigned master3_reset : 1;
   unsigned master4_reset : 1;
   unsigned master5_reset : 1;
   unsigned master6_reset : 1;
   unsigned unused0 : 9;
   unsigned macro_tlb_reset : 1;
   unsigned ptw_cache_reset : 1;
   unsigned unused1 : 13;
   unsigned iommu_reset : 1;
  } b;
   unsigned long w;
} IOMMU_RESET_REG
Allwinner H616 Manual