Регистры H616: NDFC DDR2 Specific Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 16

DLEN_WR

Bits 15 : 12
R/W
0x0

The number of latency DQS cycle for write
0000: No latency
0001: One latency DQS cycle
0010: Two latency DQS cycle
0011: Four latency DQS cycle

DLEN_RD

Bits 11 : 8
R/W
0x0

The number of latency DQS cycle for read
0000: No latency
0001: One latency DQS cycle
0010: Two latency DQS cycle
0011: Four latency DQS cycle

Unused

Bits 7 : 3

EN_RE_C

Bit 2
R/W
0x0

Enable the complementary RE# signal
0: Disable
1: Enable

EN_DQS_C

Bit 1
R/W
0x0

Enable the complementary DQS signal
0: Disable
1: Enable

Unused

Bit 0

Bit fields structure

typedef union ndfc_ddr2_spec_ctl { struct { unsigned unused0 : 1; unsigned en_dqs_c : 1; unsigned en_re_c : 1; unsigned unused1 : 5; unsigned dlen_rd : 4; unsigned dlen_wr : 4; unsigned unused2 : 16; } b; unsigned long w; } NDFC_DDR2_SPEC_CTL