Регистры H616: NDFC Normal DMA Mode Control Register

NDFC_NDMA_MODE_CTL

5.2.5. NDFC Normal DMA Mode Control Register - адрес: 0x4011120 (смещение: 0x0120)

Контроллер Nand Flash (NDFC): список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 8

DMA_ACT_STA

Bits 7 : 6
R/W
0x11

00:dma_active is low
01:dma_active is high
10:dma_active is controlled by dma_request(DRQ)
11:dma_active is controlled by controller

DMA_ACK_EN

Bit 5
R/W
0x1

0: active fall do not care ack
1: active fall must after detect ack is high

DELAY_CYCLE

Bits 4 : 0
R/W
0x05

The counts of hold cycles from DMA last signal high to dma_active high

Bit fields structure

typedef union ndfc_ndma_mode_ctl { struct { unsigned delay_cycle : 5; unsigned dma_ack_en : 1; unsigned dma_act_sta : 2; unsigned unused0 : 24; } b; unsigned long w; } NDFC_NDMA_MODE_CTL