Модуль управления памятью ввода-вывода IOMMU: список регистров

  Unused

  MASTER6_BYPASS

Master6 bypass switch
After bypass function is opened, IOMMU can not map the address of
Master6 sending, and directly output the virtual address to MBUS as
physical address.
0: Disable bypass function
1: Enable bypass function

  MASTER5_BYPASS

Master5 bypass switch
After bypass function is opened, IOMMU can not map the address of
Master5 sending, and directly output the virtual address to MBUS as
physical address.
0: Disable bypass function
1: Enable bypass function

  MASTER4_BYPASS

Master4 bypass switch
After bypass function is opened, IOMMU can not map the address of
Master4 sending, and directly output the virtual address to MBUS as
physical address.
0: Disable bypass function
1: Enable bypass function

  MASTER3_BYPASS

Master3 bypass switch
After bypass function is opened, IOMMU can not map the address of
Master3 sending, and directly output the virtual address to MBUS as
physical address.
0: Disable bypass function
1: Enable bypass function

  MASTER2_BYPASS

Master2 bypass switch
After bypass function is opened, IOMMU can not map the address of
Master2 sending, and directly output the virtual address to MBUS as
physical address.
0: Disable bypass function
1: Enable bypass function

  MASTER1_BYPASS

Master1 bypass switch
After bypass function is opened, IOMMU can not map the address of
Master1 sending, and directly output the virtual address to MBUS as
physical address.
0: Disable bypass function
1: Enable bypass function

  MASTER0_BYPASS

Master0 bypass switch
After bypass function is opened, IOMMU can not map the address of
Master0 sending, and directly output the virtual address to MBUS as
physical address.
0: Disable bypass function
1: Enable bypass function

Note
Operating the register belongs to non-accurate timing sequence control function. That is, before the function is valid, master operation will complete address mapping function, and after the operation will not perform address mapping. It is suggested that master is in reset state or in no any bus operation before operating the register .

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  iommu_bypass_reg
{
  struct
  {
   unsigned master0_bypass : 1;
   unsigned master1_bypass : 1;
   unsigned master2_bypass : 1;
   unsigned master3_bypass : 1;
   unsigned master4_bypass : 1;
   unsigned master5_bypass : 1;
   unsigned master6_bypass : 1;
   unsigned unused0 : 25;
  } b;
   unsigned long w;
} IOMMU_BYPASS_REG