Регистры H616: Clock Control Register

SMHC_CLKDIV

5.3.5. Clock Control Register - адрес: 0x4020004 0x4021004 0x4022004 (смещение: 0x0004)

Хост-контроллер SD / MMC (SMHC): список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

MASK_DATA0

Bit 31
R/W
0x0

0: Do not mask data0 when update clock
1: Mask data0 when update clock

Unused

Bits 30 : 18

CCLK_CTRL

Bit 17
R/W
0x0

Card Clock Output Control
0: Card clock always on
1: Turn off card clock when FSM is in IDLE state

CCLK_ENB

Bit 16
R/W
0x0

Card Clock Enable
0: Card Clock off
1: Card Clock on

Unused

Bits 15 : 8

CCLK_DIV

Bits 7 : 0
R/W
0x0

Card Clock Divider
Source clock is divided by 2*n (n=0~255) when HS400_MD_EN is set, this field must be cleared.

Bit fields structure

typedef union smhc_clkdiv { struct { unsigned cclk_div : 8; unsigned unused0 : 8; unsigned cclk_enb : 1; unsigned cclk_ctrl : 1; unsigned unused1 : 13; unsigned mask_data0 : 1; } b; unsigned long w; } SMHC_CLKDIV