Регистры H616: SD New Timing Set Register (Only for SMHC0, SMHC1)

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

MODE_SELEC

Bit 31
R/W
0x1

0: Old mode of Sample/Output Timing
1: New mode of Sample/Output Timing

Unused

Bits 30 : 28

DAT0_BYPASS

Bit 27
R/W
0x0

Select data0 input asyn or bypass sample logic, it is used to check card busy or not.

0: Enable data0 bypass
1: Disable data0 bypass

Unused

Bits 26 : 25

CMD_DAT_RX_PHASE_CLR

Bit 24
R/W
0x1

Clear command lines and data lines input phase during update clock operation.

0: Disable
1: Enable

Unused

Bit 23

DAT_CRC_STATUS_RX_PHASE_CLR

Bit 22
R/W
0x1

Clear data lines input phase before receive CRC status.
0: Disable
1: Enable

DAT_TRANS_RX_PHASE_CLR

Bit 21
R/W
0x1

Clear data lines input phase before transfer data.
0: Disable
1: Enable

DAT_RECV_RX_PHASE_CLR

Bit 20
R/W
0x1

Clear data lines input phase before receive data.
0: Disable
1: Enable

Unused

Bits 19 : 17

CMD_SEND_RX_PHASE_CLR

Bit 16
R/W
0x1

Clear command rx phase before send command.
0: Disable
1: Enable

Unused

Bits 15 : 10

DAT_SAMPLE_TIMING_PHASE

Bits 9 : 8
R/W
0x0

00: Sample timing phase offset 900
01: Sample timing phase offset 1800
10: Sample timing phase offset 2700
11: Ignore

Unused

Bits 7 : 6

CMD_SAMPLE_TIMING_PHASE

Bits 5 : 4
R/W
0x0

00: Sample timing phase offset 900
01: Sample timing phase offset 1800
10: Sample timing phase offset 2700
11: Ignore

Note
This register is valid for SMHC0,SMHC1.

Unused

Bits 3 : 0

Bit fields structure

typedef union smhc_ntsr { struct { unsigned unused0 : 4; unsigned cmd_sample_timing_phase : 2; unsigned unused1 : 2; unsigned dat_sample_timing_phase : 2; unsigned unused2 : 6; unsigned cmd_send_rx_phase_clr : 1; unsigned unused3 : 3; unsigned dat_recv_rx_phase_clr : 1; unsigned dat_trans_rx_phase_clr : 1; unsigned dat_crc_status_rx_phase_clr : 1; unsigned unused4 : 1; unsigned cmd_dat_rx_phase_clr : 1; unsigned unused5 : 2; unsigned dat0_bypass : 1; unsigned unused6 : 3; unsigned mode_selec : 1; } b; unsigned long w; } SMHC_NTSR