Регистры H616: IDMAC Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

DES_LOAD_CTRL

Bit 31
W
0x0

When IDMAC fetches a descriptor, if the valid bit of a descriptor is not set,
IDMAC FSM will go to the suspend state. Setting this bit will make IDMAC
refetch descriptor again and do the transfer normally.

Unused

Bits 30 : 11

RESERVED1

Bits 10 : 8
R
0x0

Reserved

IDMAC_ENB

Bit 7
R/W
0x0

IDMAC Enable
When set, the IDMAC is enabled.

RESERVED2

Bits 6 : 2
R/W
0x0

Reserved

FIX_BUST_CTRL

Bit 1
R/W
0x0

Fixed Burst
Controls whether the AHB Master interface performs fixed burst transfers or
not. When set, the AHB will use only SINGLE, INCR4, INCR8 during start of
normal burst transfers. When reset, the AHB will use SINGLE and INCR burst
transfer operations.

IDMAC_RST

Bit 0
R/W
0x0

DMA Reset
When set, the DMA Controller resets all its internal registers. SWR is
read/write. It is automatically cleared after 1 clock cycle.

Bit fields structure

typedef union smhc_idmac { struct { unsigned idmac_rst : 1; unsigned fix_bust_ctrl : 1; unsigned reserved2 : 5; unsigned idmac_enb : 1; unsigned reserved1 : 3; unsigned unused0 : 20; unsigned des_load_ctrl : 1; } b; unsigned long w; } SMHC_IDMAC