Unused Bits 31 : 17
RESERVED1 Bits 16 : 13
R
0x0
Reserved
IDMAC_ERR_STA Bits 12 : 10
R
0x0
Error Bits
Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus
Error bit (IDSTS[2]) set. This field does not generate an interrupt.
001: Host Abort received during transmission
010: Host Abort received during reception
Others: Reserved
The bit is read-only.
ABN_INT_SUM_AIS Bit 9
R/W1C
0x0
Abnormal Interrupt Summary
Logical OR of the following:
IDSTS[2]: Fatal Bus Interrupt
IDSTS[4]: Descriptor Unavailable bit Interrupt
IDSTS[5]: Card Error Summary Interrupt
Only unmasked bits affect this bit.
This is a sticky bit and must be cleared each time a corresponding bit that
causes AIS to be set is cleared. Writing a 1 clears this bit.
NOR_INT_SUM_NIS Bit 8
R/W1C
0x0
Normal Interrupt Summary
Logical OR of the following:
IDSTS[0]: Transmit Interrupt
IDSTS[1]: Receive Interrupt
Only unmasked bits affect this bit.
This is a sticky bit and must be cleared each time a corresponding bit that
causes NIS to be set is cleared. Writing a 1 clears this bit.
Unused Bits 7 : 6
ERR_FLAG_SUM Bit 5
R/W1C
0x0
Card Error Summary
Indicates the status of the transaction to/from the card; also present in RINT-STS.
Indicates the logical OR of the following bits:
EBE: End Bit Error
RTO: Response Timeout/Boot ACK Timeout
RCRC: Response CRC
SBE: Start Bit Error
DRTO: Data Read Timeout/BDS timeout
DCRC: Data CRC for Receive
RE: Response Error
Writing a 1 clears this bit.
DES_UNAVL_INT Bit 4
R/W1C
0x0
Descriptor Unavailable Interrupt
This bit is set when the descriptor is unavailable due to OWN bit = 0
(DES0[31] =0).
Writing a 1 clears this bit.
Unused Bit 3
FATAL_BERR_INT Bit 2
R/W1C
0x0
Fatal Bus Error Interrupt
Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the
DMA disables all its bus accesses.
Writing a 1 clears this bit.
RX_INT Bit 1
R/W1C
0x0
Receive Interrupt
Indicates the completion of data reception for a descriptor.
Writing a 1 clears this bit.
TX_INT Bit 0
R/W1C
0x0
Transmit Interrupt
Indicates that data transmission is finished for a descriptor.
Writing a 1 clears this bit.
Команда U-Boot для чтения регистра md 4020088 1 md 4021088 1 md 4022088 1
Bit fields structure
typedef union smhc_idst
{
struct
{
unsigned tx_int : 1;
unsigned rx_int : 1;
unsigned fatal_berr_int : 1;
unsigned unused0 : 1;
unsigned des_unavl_int : 1;
unsigned err_flag_sum : 1;
unsigned unused1 : 2;
unsigned nor_int_sum_nis : 1;
unsigned abn_int_sum_ais : 1;
unsigned idmac_err_sta : 3;
unsigned reserved1 : 4;
unsigned unused2 : 15;
} b;
unsigned long w;
} SMHC_IDST
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