Регистры H616: IDMAC Interrupt Enable Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 10

RESERVED1

Bits 9 : 8
R/W
0x0

Reserved

Unused

Bits 7 : 6

ERR_SUM_INT_ENB

Bit 5
R/W
0x0

Card Error Summary Interrupt Enable.
When setting, it enables the Card Interrupt Summary.

DES_UNAVL_INT_ENB

Bit 4
R/W
0x0

Descriptor Unavailable Interrupt.
When setting along with Abnormal Interrupt Summary Enable, the
Descriptor Unavailable interrupt is enabled.

Unused

Bit 3

FERR_INT_ENB

Bit 2
R/W
0x0

Fatal Bus Error Enable
When setting with Abnormal Interrupt Summary Enable, the Fatal Bus Error
Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled.

RX_INT_ENB

Bit 1
R/W
0x0

Receive Interrupt Enable.
When setting with Normal Interrupt Summary Enable, Receive Interrupt is
enabled. When reset, Receive Interrupt is disabled.

TX_INT_ENB

Bit 0
R/W
0x0

Transmit Interrupt Enable.
When setting with Normal Interrupt Summary Enable, Transmit Interrupt is
enabled. When reset, Transmit Interrupt is disabled.

Bit fields structure

typedef union smhc_idie { struct { unsigned tx_int_enb : 1; unsigned rx_int_enb : 1; unsigned ferr_int_enb : 1; unsigned unused0 : 1; unsigned des_unavl_int_enb : 1; unsigned err_sum_int_enb : 1; unsigned unused1 : 2; unsigned reserved1 : 2; unsigned unused2 : 22; } b; unsigned long w; } SMHC_IDIE