Регистры H616: eMMC4.5 DDR Start Bit Detection Control Register

EMMC_DDR_SBIT_DET

5.3.5. eMMC4.5 DDR Start Bit Detection Control Register - адрес: 0x402010c 0x402110c 0x402210c (смещение: 0x010C)

Хост-контроллер SD / MMC (SMHC): список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

HS400_MD_EN

Bit 31
R/W
0x0

HS400 Mode Enable (for SMHC2 only)
0: Disable
1: Enable
It is required to set this bit to 1 before initiating any data transfer CMD in HS400 mode.

Unused

Bits 30 : 1

HALF_START_BIT

Bit 0
R/W
0x0

Control for start bit detection mechanism inside mstorage based on duration of start bit.
For eMMC 4.5, start bit can be:
0: Full cycle
1: Less than one full cycle
Set HALF_START_BIT=1 for eMMC 4.5 and above; set to 0 for SD applications.

Bit fields structure

typedef union emmc_ddr_sbit_det { struct { unsigned half_start_bit : 1; unsigned unused0 : 30; unsigned hs400_md_en : 1; } b; unsigned long w; } EMMC_DDR_SBIT_DET