Хост-контроллер SD / MMC (SMHC): список регистров

  Unused

  DAT_DRV_PH_SEL

Data Drive Phase Select
For SMHC0,SMHC1:
0: Data drive phase offset is 900 at SDR mode, 450 at DDR mode
1: Data drive phase offset is 1800 at SDR mode, 900 at DDR mode
For SMHC2:
0: Data drive phase offset is 900 at SDR mode, 450 at DDR8 mode, 900 at
DDR4/HS400 mode
1: Data drive phase offset is 1800 at SDR mode, 900 at DDR8 mode, 00 at
DDR4/HS400 mode

  CMD_DRV_PH_SEL

Command Drive Phase Select
For SMHC0,SMHC1:
0: Command drive phase offset is 900 at SDR mode, 450 at DDR mode
1: Command drive phase offset is 1800 at SDR mode, 900 at DDR mode
For SMHC2:
0: Command drive phase offset is 900 at SDR mode, 450 at DDR8 mode, 900 at
DDR4/HS400 mode
1: Command drive phase offset is 1800 at SDR mode, 900 at DDR8 mode, 1800 at DDR4/HS400 mode

  Unused

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  smhc_drv_dl
{
  struct
  {
   unsigned unused0 : 16;
   unsigned cmd_drv_ph_sel : 1;
   unsigned dat_drv_ph_sel : 1;
   unsigned unused1 : 14;
  } b;
   unsigned long w;
} SMHC_DRV_DL