Регистры H616: Sample Delay Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 16

SAMP_DL_CAL_START

Bit 15
R/W
0x0

Sample Delay Calibration Start
When set, start sample delay chain calibration.

SAMP_DL_CAL_DONE

Bit 14
R
0x0

Sample Delay Calibration Done
When set, it means that sample delay chain calibration is done and the result
of calibration is shown in SAMP_DL.

SAMP_DL

Bits 13 : 8
R
0x20

Sample Delay
It indicates the number of delay cells corresponding to current card clock.
The delay time generated by these delay cells is equal to the cycle of card
clock nearly.
Generally, it is necessary to do drive delay calibration when card clock is
changed.
This bit is valid only when SAMP_DL_CAL_DONE is set.

SAMP_DL_SW_EN

Bit 7
R/W
0x0

Sample Delay Software Enable
When set, enable sample delay specified at SAMP_DL_SW

Unused

Bit 6

SAMP_DL_SW

Bits 5 : 0
R/W
0x0

Sample Delay Software
The relative delay between clock line and command line, data lines.
It can be determined according to the value of SAMP_DL, the cycle of card
clock and device's input timing requirement.

Bit fields structure

typedef union smhc_samp_dl { struct { unsigned samp_dl_sw : 6; unsigned unused0 : 1; unsigned samp_dl_sw_en : 1; unsigned samp_dl : 6; unsigned samp_dl_cal_done : 1; unsigned samp_dl_cal_start : 1; unsigned unused1 : 16; } b; unsigned long w; } SMHC_SAMP_DL