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EMAC_INT_STA
6.1. EMAC Interrupt Status Register - адрес: 0x5020008 0x5030008 (смещение: 0x0008)

Контроллер Ethernet: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

  Unused

Bits 31 : 17

  RGMII_LINK_STA_P

Bit 16
R/W1C
0x0

R MII Link Status Changed Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it.

  Unused

Bits 15 : 14

  RX_EARLY_P

Bit 13
R/W1C
0x0

RX DMA Filled First data Buffer of the Receive Frame Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it.

  RX_OVERFLOW_P

Bit 12
R/W1C
0x0

RX FIFO Overflow Error Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it.

  RX_TIMEOUT_P

Bit 11
R/W1C
0x0

RX Timeout Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it. When this bit asserted, the length of receive frame is
greater than 2048 bytes (10240 when JUMBO_FRM_EN is set)

  RX_DMA_STOPPED_P

Bit 10
R/W1C
0x0

When this bit asserted, the RX DMA FSM is stopped.

  RX_BUF_UA_P

Bit 9
R/W1C
0x0

RX Buffer UA Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it. When this asserted, the RX DMA cannot acquire next RX
descriptor and RX DMA FSM is suspended. The ownership of next RX
descriptor should be changed to RX DMA. The RX DMA FSM will resume
when writing to RX_DMA_START bit or next receive frame is coming.

  RX_P

Bit 8
R/W1C
0x0

Frame RX Completed Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it. When this bit is asserted, a frame reception is completed.
The RX DMA FSM remains in the running state.

  Unused

Bits 7 : 6

  TX_EARLY_P

Bit 5
R/W1C
0x0

Frame is transmitted to FIFO totally Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it.

  TX_UNDERFLOW_P

Bit 4
R/W1C
0x0

TX FIFO Underflow Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it.

  TX_TIMEOUT_P

Bit 3
R/W1C
0x0

Transmitter Timeout Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it.

  TX_BUF_UA_P

Bit 2
R/W1C
0x0

TX Buffer UA Interrupt Pending
0: No Pending
1: Pending
When this asserted, the TX DMA can not acquire next TX descriptor and TX
DMA FSM is suspended. The ownership of next TX descriptor should be
changed to TX DMA. The TX DMA FSM will resume when writing to TX_DMA_START bit.

  TX_DMA_STOPPED_P

Bit 1
R/W1C
0x0

Transmission DMA Stopped Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it.

  TX_P

Bit 0
R/W1C
0x0

Frame Transmission Interrupt Pending
0: No Pending
1: Pending
Write 1 to clear it.

Команда U-Boot для чтения регистра

md 5020008 1
md 5030008 1

Bit fields structure 

typedef union  emac_int_sta
{
  struct
  {
   unsigned tx_p : 1;
   unsigned tx_dma_stopped_p : 1;
   unsigned tx_buf_ua_p : 1;
   unsigned tx_timeout_p : 1;
   unsigned tx_underflow_p : 1;
   unsigned tx_early_p : 1;
   unsigned unused0 : 2;
   unsigned rx_p : 1;
   unsigned rx_buf_ua_p : 1;
   unsigned rx_dma_stopped_p : 1;
   unsigned rx_timeout_p : 1;
   unsigned rx_overflow_p : 1;
   unsigned rx_early_p : 1;
   unsigned unused1 : 2;
   unsigned rgmii_link_sta_p : 1;
   unsigned unused2 : 15;
  } b;
   unsigned long w;
} EMAC_INT_STA
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