Регистры H616: EMAC Transmit Control Register1

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

TX_DMA_START

Bit 31
R/W
0x0

Transmit DMA FSM Start
0: No valid
1: Start
It is cleared internally and always read a 0

TX_DMA_EN

Bit 30
R/W
0x0

0: Stop TX DMA after the completion of current frame transmission.
1: Start and run TX DMA.

Unused

Bits 29 : 11

TX_TH

Bits 10 : 8
R/W
0x0

Threshold value of TX DMA FIFO
When TX_MD is 0, transmission starts when the size of frame in TX DMA FIFO
is greater than the threshold. In addition, full frames with a length less than
the threshold are transferred automatically.
000: 64
001: 128
010: 192
011: 256
Others: Reserved

Unused

Bits 7 : 2

TX_MD

Bit 1
R/W
0x0

Transmission Mode
0: TX start after TX DMA FIFO bytes is greater than TX_TH
1: TX start after TX DMA FIFO located a full frame

FLUSH_TX_FIFO

Bit 0
R/W
0x0

Flush the data in the TX FIFO
0: Enable
1: Disable

Bit fields structure

typedef union emac_tx_ctl1 { struct { unsigned flush_tx_fifo : 1; unsigned tx_md : 1; unsigned unused0 : 6; unsigned tx_th : 3; unsigned unused1 : 19; unsigned tx_dma_en : 1; unsigned tx_dma_start : 1; } b; unsigned long w; } EMAC_TX_CTL1