IOMMU_TLB_ENABLE_REG Модуль управления памятью ввода-вывода IOMMU: список регистров 31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16 15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00 Unused Bits 31 : 18PTW_CACHE_ENABLE Bit 17R/W 0x1 PTW Cache enable bit MACRO_TLB_ENABLE Bit 16R/W 0x1 Macro TLB enable bit Unused Bits 15 : 7MICRO_TLB6_ENABLE Bit 6R/W 0x1 Micro TLB6 enable bit MICRO_TLB5_ENABLE Bit 5R/W 0x1 Micro TLB5 enable bit MICRO_TLB4_ENABLE Bit 4R/W 0x1 Micro TLB4 enable bit MICRO_TLB3_ENABLE Bit 3R/W 0x1 Micro TLB3 enable bit MICRO_TLB2_ENABLE Bit 2R/W 0x1 Micro TLB2 enable bit MICRO_TLB1_ENABLE Bit 1R/W 0x1 Micro TLB1 enable bit MICRO_TLB0_ENABLE Bit 0R/W 0x1 Micro TLB0 enable bit Команда U-Boot для чтения регистра md 30f0060 1Bit fields structuretypedef union iommu_tlb_enable_reg { struct { unsigned micro_tlb0_enable : 1; unsigned micro_tlb1_enable : 1; unsigned micro_tlb2_enable : 1; unsigned micro_tlb3_enable : 1; unsigned micro_tlb4_enable : 1; unsigned micro_tlb5_enable : 1; unsigned micro_tlb6_enable : 1; unsigned unused0 : 9; unsigned macro_tlb_enable : 1; unsigned ptw_cache_enable : 1; unsigned unused1 : 14; } b; unsigned long w; } IOMMU_TLB_ENABLE_REG |
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