Модуль управления памятью ввода-вывода IOMMU: список регистров

  Unused

  PTW_CACHE_FLUSH

Clear PTW Cache
0: No clear operation or clear operation completed
1: Enable is cleared
After Flush operation completes, the bit can clear 0 automatically.

  MACRO_TLB_FLUSH

Clear Macro TLB
0: No clear operation or clear operation completed
1: Enable is cleared
After Flush operation completes, the bit can clear 0 automatically.

  Unused

  MICRO_TLB6_FLUSH

Clear Micro TLB6
0: No clear operation or clear operation completed
1: Enable is cleared
After Flush operation completes, the bit can clear 0 automatically.

  MICRO_TLB5_FLUSH

Clear Micro TLB5
0: No clear operation or clear operation completed
1: Enable is cleared
After Flush operation completes, the bit can clear 0 automatically.

  MICRO_TLB4_FLUSH

Clear Micro TLB4
0: No clear operation or clear operation completed
1: Enable is cleared
After Flush operation completes, the bit can clear 0 automatically.

  MICRO_TLB3_FLUSH

Clear Micro TLB3
0: No clear operation or clear operation completed
1: Enable is cleared
After Flush operation completes, the bit can clear 0 automatically.

  MICRO_TLB2_FLUSH

Clear Micro TLB2
0: No clear operation or clear operation completed
1: Enable is cleared
After Flush operation completes, the bit can clear 0 automatically.

  MICRO_TLB1_FLUSH

Clear Micro TLB1
0: No clear operation or clear operation completed
1: Enable is cleared
After Flush operation completes, the bit can clear 0 automatically.

  MICRO_TLB0_FLUSH

Clear Micro TLB1
0: No clear operation or clear operation completed
1: Enable is cleared
After Flush operation completes, the bit can clear 0 automatically.

Note
When performing flush operation, all TLB/Cache access will be paused.
Before flush starts, the operation that has entered TLB continues to complete.

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  iommu_tlb_flush_enable_reg
{
  struct
  {
   unsigned micro_tlb0_flush : 1;
   unsigned micro_tlb1_flush : 1;
   unsigned micro_tlb2_flush : 1;
   unsigned micro_tlb3_flush : 1;
   unsigned micro_tlb4_flush : 1;
   unsigned micro_tlb5_flush : 1;
   unsigned micro_tlb6_flush : 1;
   unsigned unused0 : 9;
   unsigned macro_tlb_flush : 1;
   unsigned ptw_cache_flush : 1;
   unsigned unused1 : 14;
  } b;
   unsigned long w;
} IOMMU_TLB_FLUSH_ENABLE_REG