Регистры H616: TV Encoder DAC CFG0 Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

DAC_CLOCK_INVERT

Bit 31
R/W
0x1

0: Not invert
1: Invert

Unused

Bits 30 : 26

CALI_IN

Bits 25 : 16
R/W
0x0

LOW_BIAS

Bits 15 : 12
R/W
0x4

500uA to 4mA

Unused

Bits 11 : 10

BIAS_EXT_SEL

Bit 9
R/W
0x1

0: disable
1: enable
(A_SEL_BIAS_ADDA)

BIAS_INT_SEL

Bit 8
R/W
0x0

0: disable
1: enable
(A_SEL_BIAS_RES)

Unused

Bits 7 : 5

BIAS_REF_INT_EN

Bit 4
R/W
0x0

0: disable
1: enable
(A_EN_RESREF)

Unused

Bits 3 : 1

DAC_EN

Bit 0
R/W
0x0

0: Disable
1: Enable

Bit fields structure

typedef union tve_dac_cfg0 { struct { unsigned dac_en : 1; unsigned unused0 : 3; unsigned bias_ref_int_en : 1; unsigned unused1 : 3; unsigned bias_int_sel : 1; unsigned bias_ext_sel : 1; unsigned unused2 : 2; unsigned low_bias : 4; unsigned cali_in : 10; unsigned unused3 : 5; unsigned dac_clock_invert : 1; } b; unsigned long w; } TVE_DAC_CFG0