Регистры H616: I2Sn Clock Divide

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 9

MCLKO_EN

Bit 8
R/W
0x0

0: Disable MCLK Output
1: Enable MCLK Output

BCLKDIV

Bits 7 : 4
R/W
0x0

BCLK Divide Ratio from PLL_Audio
0000: reserved
0001: Divide by 1
0010: Divide by 2
0011: Divide by 4
0100: Divide by 6
0101: Divide by 8
0110: Divide by 12
0111: Divide by 16
1000: Divide by 24
1001: Divide by 32
1010: Divide by 48
1011: Divide by 64
1100: Divide by 96
1101: Divide by 128
1110: Divide by 176
1111: Divide by 192

MCLKDIV

Bits 3 : 0
R/W
0x0

MCLK Divide Ratio from PLL_Audio
0000: reserved
0001: Divide by 1
0010: Divide by 2
0011: Divide by 4
0100: Divide by 6
0101: Divide by 8
0110: Divide by 12
0111: Divide by 16
1000: Divide by 24
1001: Divide by 32
1010: Divide by 48
1011: Divide by 64
1100: Divide by 96
1101: Divide by 128
1110: Divide by 176
1111: Divide by 192

Bit fields structure

typedef union i2sn_clkd { struct { unsigned mclkdiv : 4; unsigned bclkdiv : 4; unsigned mclko_en : 1; unsigned unused0 : 23; } b; unsigned long w; } I2Sn_CLKD