Регистры Allwinner H616
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IOMMU_DM_AUT_CTRL_REG0
3.12.5. IOMMU Domain Authority Control Register 0 - адрес: 0x30f00b0 (смещение: 0x00B0)

Модуль управления памятью ввода-вывода IOMMU: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

  Unused

Bits 31 : 30

  DM1_M6_WT_AUT_CTRL

Bit 29
R/W
0x0

Domain1 write permission control for master6
0: The write-operation is permitted
1: The write-operation is prohibited

  DM1_M6_RD_AUT_CTRL

Bit 28
R/W
0x0

Domain1 read permission control for master6
0: The read-operation is permitted
1: The read-operation is prohibited

  DM1_M5_WT_AUT_CTRL

Bit 27
R/W
0x0

Domain1 write permission control for master5
0: The write-operation is permitted
1: The write-operation is prohibited

  DM1_M5_RD_AUT_CTRL

Bit 26
R/W
0x0

Domain1 read permission control for master5
0: The read-operation is permitted
1: The read-operation is prohibited

  DM1_M4_WT_AUT_CTRL

Bit 25
R/W
0x0

Domain1 write permission control for master4
0: The write-operation is permitted
1: The write-operation is prohibited

  DM1_M4_RD_AUT_CTRL

Bit 24
R/W
0x0

Domain1 read permission control for master4
0: The read-operation is permitted
1: The read-operation is prohibited

  DM1_M3_WT_AUT_CTRL

Bit 23
R/W
0x0

Domain1 write permission control for master3
0: The write-operation is permitted
1: The write-operation is prohibited

  DM1_M3_RD_AUT_CTRL

Bit 22
R/W
0x0

Domain1 read permission control for master3
0: The read-operation is permitted
1: The read-operation is prohibited

  DM1_M2_WT_AUT_CTRL

Bit 21
R/W
0x0

Domain1 write permission control for master2
0: The write-operation is permitted
1: The write-operation is prohibited

  DM1_M2_RD_AUT_CTRL

Bit 20
R/W
0x0

Domain1 read permission control for master2
0: The read-operation is permitted
1: The read-operation is prohibited

  DM1_M1_WT_AUT_CTRL

Bit 19
R/W
0x0

Domain1 write permission control for master1
0: The write-operation is permitted
1: The write-operation is prohibited

  DM1_M1_RD_AUT_CTRL

Bit 18
R/W
0x0

Domain1 read permission control for master1
0: The read-operation is permitted
1: The read-operation is prohibited

  DM1_M0_WT_AUT_CTRL

Bit 17
R/W
0x0

Domain1 write permission control for master0
0: The write-operation is permitted
1: The write-operation is prohibited

  DM1_M0_RD_AUT_CTRL

Bit 16
R/W
0x0

Domain1 read permission control for master0
0: The read-operation is permitted
1: The read-operation is prohibited

  Unused

Bits 15 : 14

  DM0_M6_WT_AUT_CTRL

Bit 13
R
0x0

Domain0 write permission control for master6
0: The write-operation is permitted
1: The write-operation is prohibited

  DM0_M6_RD_AUT_CTRL

Bit 12
R
0x0

Domain0 read permission control for master6
0: The read-operation is permitted
1: The read-operation is prohibited

  DM0_M5_WT_AUT_CTRL

Bit 11
R
0x0

Domain0 write permission control for master5
0: The write-operation is permitted
1: The write-operation is prohibited

  DM0_M5_RD_AUT_CTRL

Bit 10
R
0x0

Domain0 read permission control for master5
0: The read-operation is permitted
1: The read-operation is prohibited

  DM0_M4_WT_AUT_CTRL

Bit 9
R
0x0

Domain0 write permission control for master4
0: The write-operation is permitted
1: The write-operation is prohibited

  DM0_M4_RD_AUT_CTRL

Bit 8
R
0x0

Domain0 read permission control for master4
0: The read-operation is permitted
1: The read-operation is prohibited

  DM0_M3_WT_AUT_CTRL

Bit 7
R
0x0

Domain0 write permission control for master3
0: The write-operation is permitted
1: The write-operation is prohibited

  DM0_M3_RD_AUT_CTRL

Bit 6
R
0x0

Domain0 read permission control for master3
0: The read-operation is permitted
1: The read-operation is prohibited

  DM0_M2_WT_AUT_CTRL

Bit 5
R
0x0

Domain0 write permission control for master2
0: The write-operation is permitted
1: The write-operation is prohibited

  DM0_M2_RD_AUT_CTRL

Bit 4
R
0x0

Domain0 read permission control for master2
0: The read-operation is permitted
1: The read-operation is prohibited

  DM0_M1_WT_AUT_CTRL

Bit 3
R
0x0

Domain0 write permission control for master1
0: The write-operation is permitted
1: The write-operation is prohibited

  DM0_M1_RD_AUT_CTRL

Bit 2
R
0x0

Domain0 read permission control for master1
0: The read-operation is permitted
1: The read-operation is prohibited

  DM0_M0_WT_AUT_CTRL

Bit 1
R
0x0

Domain0 write permission control for master0
0: The write-operation is permitted
1: The write-operation is prohibited

  DM0_M0_RD_AUT_CTRL

Bit 0
R
0x0

Domain0 read permission control for master0
0: The read-operation is permitted
1: The read-operation is prohibited

Note
Software can be set up 15 different permission control types , which are set in IOMMU_DM_AUT_CTRL_REG0 ~ 7.
As well as a default access control type, domain0.
The read/write operation of DOMIAN1 ~ 15 is unlimited by default.
Software needs to set the corresponding permission control domain index of the page table item
in the secondary page table entries[7:4], the default value is 0, use domian0,
namely the read/write operation is not controlled.
Setting REG_ARD_OVWT can mask the Domain control defined by IOMMU_DM_AUT_CTRL_REG0~7.
All Level2 page table type are covered by the type of REG_ARD_OVWT.
The read/write operation is permitted by default.

Команда U-Boot для чтения регистра

md 30f00b0 1

Bit fields structure 

typedef union  iommu_dm_aut_ctrl_reg0
{
  struct
  {
   unsigned dm0_m0_rd_aut_ctrl : 1;
   unsigned dm0_m0_wt_aut_ctrl : 1;
   unsigned dm0_m1_rd_aut_ctrl : 1;
   unsigned dm0_m1_wt_aut_ctrl : 1;
   unsigned dm0_m2_rd_aut_ctrl : 1;
   unsigned dm0_m2_wt_aut_ctrl : 1;
   unsigned dm0_m3_rd_aut_ctrl : 1;
   unsigned dm0_m3_wt_aut_ctrl : 1;
   unsigned dm0_m4_rd_aut_ctrl : 1;
   unsigned dm0_m4_wt_aut_ctrl : 1;
   unsigned dm0_m5_rd_aut_ctrl : 1;
   unsigned dm0_m5_wt_aut_ctrl : 1;
   unsigned dm0_m6_rd_aut_ctrl : 1;
   unsigned dm0_m6_wt_aut_ctrl : 1;
   unsigned unused0 : 2;
   unsigned dm1_m0_rd_aut_ctrl : 1;
   unsigned dm1_m0_wt_aut_ctrl : 1;
   unsigned dm1_m1_rd_aut_ctrl : 1;
   unsigned dm1_m1_wt_aut_ctrl : 1;
   unsigned dm1_m2_rd_aut_ctrl : 1;
   unsigned dm1_m2_wt_aut_ctrl : 1;
   unsigned dm1_m3_rd_aut_ctrl : 1;
   unsigned dm1_m3_wt_aut_ctrl : 1;
   unsigned dm1_m4_rd_aut_ctrl : 1;
   unsigned dm1_m4_wt_aut_ctrl : 1;
   unsigned dm1_m5_rd_aut_ctrl : 1;
   unsigned dm1_m5_wt_aut_ctrl : 1;
   unsigned dm1_m6_rd_aut_ctrl : 1;
   unsigned dm1_m6_wt_aut_ctrl : 1;
   unsigned unused1 : 2;
  } b;
   unsigned long w;
} IOMMU_DM_AUT_CTRL_REG0
Allwinner H616 Manual