Регистры Allwinner H616
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IOMMU_DM_AUT_CTRL_REG2
3.12.5. IOMMU Domain Authority Control Register 2 - адрес: 0x30f00b8 (смещение: 0x00B8)

Модуль управления памятью ввода-вывода IOMMU: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

  Unused

Bits 31 : 30

  DM5_M6_WT_AUT_CTRL

Bit 29
R/W
0x0

Domain5 write permission control for master6
0: The write-operation is permitted
1: The write-operation is prohibited

  DM5_M6_RD_AUT_CTRL

Bit 28
R/W
0x0

Domain5 read permission control for master6
0: The read-operation is permitted
1: The read-operation is prohibited

  DM5_M5_WT_AUT_CTRL

Bit 27
R/W
0x0

Domain5 write permission control for master5
0: The write-operation is permitted
1: The write-operation is prohibited

  DM5_M5_RD_AUT_CTRL

Bit 26
R/W
0x0

Domain5 read permission control for master5
0: The read-operation is permitted
1: The read-operation is prohibited

  DM5_M4_WT_AUT_CTRL

Bit 25
R/W
0x0

Domain5 write permission control for master4
0: The write-operation is permitted
1: The write-operation is prohibited

  DM5_M4_RD_AUT_CTRL

Bit 24
R/W
0x0

Domain5 read permission control for master4
0: The read-operation is permitted
1: The read-operation is prohibited

  DM5_M3_WT_AUT_CTRL

Bit 23
R/W
0x0

Domain5 write permission control for master3
0: The write-operation is permitted
1: The write-operation is prohibited

  DM5_M3_RD_AUT_CTRL

Bit 22
R/W
0x0

Domain5 read permission control for master3
0: The read-operation is permitted
1: The read-operation is prohibited

  DM5_M2_WT_AUT_CTRL

Bit 21
R/W
0x0

Domain5 write permission control for master2
0: The write-operation is permitted
1: The write-operation is prohibited

  DM5_M2_RD_AUT_CTRL

Bit 20
R/W
0x0

Domain5 read permission control for master2
0: The read-operation is permitted
1: The read-operation is prohibited

  DM5_M1_WT_AUT_CTRL

Bit 19
R/W
0x0

Domain5 write permission control for master1
0: The write-operation is permitted
1: The write-operation is prohibited

  DM5_M1_RD_AUT_CTRL

Bit 18
R/W
0x0

Domain5 read permission control for master1
0: The read-operation is permitted
1: The read-operation is prohibited

  DM5_M0_WT_AUT_CTRL

Bit 17
R/W
0x0

Domain5 write permission control for master0
0: The write-operation is permitted
1: The write-operation is prohibited

  DM5_M0_RD_AUT_CTRL

Bit 16
R/W
0x0

Domain5 read permission control for master0
0: The read-operation is permitted
1: The read-operation is prohibited

  Unused

Bits 15 : 14

  DM4_M6_WT_AUT_CTRL

Bit 13
R/W
0x0

Domain4 write permission control for master6
0: The write-operation is permitted
1: The write-operation is prohibited

  DM4_M6_RD_AUT_CTRL

Bit 12
R/W
0x0

Domain4 read permission control for master6
0: The read-operation is permitted
1: The read-operation is prohibited

  DM4_M5_WT_AUT_CTRL

Bit 11
R/W
0x0

Domain4 write permission control for master5
0: The write-operation is permitted
1: The write-operation is prohibited

  DM4_M5_RD_AUT_CTRL

Bit 10
R/W
0x0

Domain4 read permission control for master5
0: The read-operation is permitted
1: The read-operation is prohibited

  DM4_M4_WT_AUT_CTRL

Bit 9
R/W
0x0

Domain4 write permission control for master4
0: The write-operation is permitted
1: The write-operation is prohibited

  DM4_M4_RD_AUT_CTRL

Bit 8
R/W
0x0

Domain4 read permission control for master4
0: The read-operation is permitted
1: The read-operation is prohibited

  DM4_M3_WT_AUT_CTRL

Bit 7
R/W
0x0

Domain4 write permission control for master3
0: The write-operation is permitted
1: The write-operation is prohibited

  DM4_M3_RD_AUT_CTRL

Bit 6
R/W
0x0

Domain4 read permission control for master3
0: The read-operation is permitted
1: The read-operation is prohibited

  DM4_M2_WT_AUT_CTRL

Bit 5
R/W
0x0

Domain4 write permission control for master2
0: The write-operation is permitted
1: The write-operation is prohibited

  DM4_M2_RD_AUT_CTRL

Bit 4
R/W
0x0

Domain4 read permission control for master2
0: The read-operation is permitted
1: The read-operation is prohibited

  DM4_M1_WT_AUT_CTRL

Bit 3
R/W
0x0

Domain4 write permission control for master1
0: The write-operation is permitted
1: The write-operation is prohibited

  DM4_M1_RD_AUT_CTRL

Bit 2
R/W
0x0

Domain4 read permission control for master1
0: The read-operation is permitted
1: The read-operation is prohibited

  DM4_M0_WT_AUT_CTRL

Bit 1
R/W
0x0

Domain4 write permission control for master0
0: The write-operation is permitted
1: The write-operation is prohibited

  DM4_M0_RD_AUT_CTRL

Bit 0
R/W
0x0

Domain4 read permission control for master0
0: The read-operation is permitted
1: The read-operation is prohibited

Команда U-Boot для чтения регистра

md 30f00b8 1

Bit fields structure 

typedef union  iommu_dm_aut_ctrl_reg2
{
  struct
  {
   unsigned dm4_m0_rd_aut_ctrl : 1;
   unsigned dm4_m0_wt_aut_ctrl : 1;
   unsigned dm4_m1_rd_aut_ctrl : 1;
   unsigned dm4_m1_wt_aut_ctrl : 1;
   unsigned dm4_m2_rd_aut_ctrl : 1;
   unsigned dm4_m2_wt_aut_ctrl : 1;
   unsigned dm4_m3_rd_aut_ctrl : 1;
   unsigned dm4_m3_wt_aut_ctrl : 1;
   unsigned dm4_m4_rd_aut_ctrl : 1;
   unsigned dm4_m4_wt_aut_ctrl : 1;
   unsigned dm4_m5_rd_aut_ctrl : 1;
   unsigned dm4_m5_wt_aut_ctrl : 1;
   unsigned dm4_m6_rd_aut_ctrl : 1;
   unsigned dm4_m6_wt_aut_ctrl : 1;
   unsigned unused0 : 2;
   unsigned dm5_m0_rd_aut_ctrl : 1;
   unsigned dm5_m0_wt_aut_ctrl : 1;
   unsigned dm5_m1_rd_aut_ctrl : 1;
   unsigned dm5_m1_wt_aut_ctrl : 1;
   unsigned dm5_m2_rd_aut_ctrl : 1;
   unsigned dm5_m2_wt_aut_ctrl : 1;
   unsigned dm5_m3_rd_aut_ctrl : 1;
   unsigned dm5_m3_wt_aut_ctrl : 1;
   unsigned dm5_m4_rd_aut_ctrl : 1;
   unsigned dm5_m4_wt_aut_ctrl : 1;
   unsigned dm5_m5_rd_aut_ctrl : 1;
   unsigned dm5_m5_wt_aut_ctrl : 1;
   unsigned dm5_m6_rd_aut_ctrl : 1;
   unsigned dm5_m6_wt_aut_ctrl : 1;
   unsigned unused1 : 2;
  } b;
   unsigned long w;
} IOMMU_DM_AUT_CTRL_REG2
Allwinner H616 Manual