Регистры H616: DMIC RXFIFO Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

DMIC_RXFIFO_FLUSH

Bit 31
R/W1C
0x0

DMIC RXFIFO Flush
Writing 1 to flush RXFIFO, self clear to '0'

Unused

Bits 30 : 10

RXFIFO_MODE

Bit 9
R/W
0x0

RXFIFO Output Mode (Mode 0, 1)
0: Expanding '0' at LSB of RXFIFO register
1: Expanding received sample sign bit at MSB of RXFIFO register
For 24-bit received audio sample:
Mode 0: RXDATA[31:0] = {RXFIFO_O[23:0], 8'h0}
Mode 1: RXDATA[31:0] = {8{RXFIFO_O[23]}, RXFIFO_O[23:0]}
For 16-bit received audio sample:
Mode 0: RXDATA[31:0] = {RXFIFO_O[23:8], 16'h0}
Mode 1: RXDATA[31:0] = {16{RXFIFO_O[23]}, RXFIFO_O[23:8]}

SAMPLE_RESOLUTION

Bit 8
R/W
0x0

0: 16-bit
1: 24- bit

RXFIFO_TRG_LEVEL

Bits 7 : 0
R/W
0x40

RXFIFO Trigger Level (TRLV[7:0])
Interrupt and DMA request trigger level for DMIC RXFIFO normal condition
IRQ/DRQ Generated when WLEVEL > TRLV[7:0])
WLEVEL represents the number of valid samples in the DMIC RXFIFO

Bit fields structure

typedef union dmic_rxfifo_ctr { struct { unsigned rxfifo_trg_level : 8; unsigned sample_resolution : 1; unsigned rxfifo_mode : 1; unsigned unused0 : 21; unsigned dmic_rxfifo_flush : 1; } b; unsigned long w; } DMIC_RXFIFO_CTR