Регистры H616: OWA General Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 10

MCLKDIV

Bits 9 : 5
R/W
0x0

MCLK Clock Divide Ratio

MCLK Divide Ratio from PLL_AUDIO
00000: Divide by 128
00001: Divide by 2
00010: Divide by 4
00011: Divide by 6
00100: Divide by 8

00101: Divide by 10
00110: Divide by 12
00111: Divide by 14
01000: Divide by 16
01001: Divide by 18
01010: Divide by 20
01011: Divide by 22
01100: Divide by 24
***
11111: Divide by 62

Unused

Bit 4

MCLKEN

Bit 3
R/W
0x0

MCLK Enable
0: Disable
1: Enable

LOOP

Bit 2
R/W
0x0

Loop Back Test
0: Normal Mode
1: Loop Back Test
When setting to 1 , DOUT and DIN need be connected.

GEN

Bit 1
R/W
0x0

Global Enable
A disable on this bit overrides any other block or channel enables and flushes all FIFOs.
0: Disable
1: Enable

RST

Bit 0
R/W
0x0

Reset
0: Normal
1: Reset
Self clear to 0.

Bit fields structure

typedef union owa_gen_ctl { struct { unsigned rst : 1; unsigned gen : 1; unsigned loop : 1; unsigned mclken : 1; unsigned unused0 : 1; unsigned mclkdiv : 5; unsigned unused1 : 22; } b; unsigned long w; } OWA_GEN_CTL