Регистры H616: OWA FIFO Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

HUB_EN

Bit 31
R/W
0x0

Audio Hub Enable
0: Disable
1: Enable

FTX

Bit 30
R/W1C
0x0

Write 1 to flush TXFIFO, self clear to '0'.

Unused

Bits 29 : 20

TXTL

Bits 19 : 12
R/W
0x40

TX FIFO Empty Trigger Level
Interrupt and DMA request trigger level for TX FIFO normal condition.
Trigger Level = TXTL

Unused

Bits 11 : 3

TXIM

Bit 2
R/W
0x0

TXFIFO Input Mode(Mode0, 1)
0: Valid data at the MSB of TXFIFO Register
1: Valid data at the LSB of TXFIFO Register
Example for 20-bit transmitted audio sample:
Mode 0: TXFIFO[23:0] = {APB_WDATA[31:12], 4'h0}
Mode 1: TXFIFO[23:0] = {APB_WDATA[19:0], 4'h0}

Unused

Bits 1 : 0

Bit fields structure

typedef union owa_fctl { struct { unsigned unused0 : 2; unsigned txim : 1; unsigned unused1 : 9; unsigned txtl : 8; unsigned unused2 : 10; unsigned ftx : 1; unsigned hub_en : 1; } b; unsigned long w; } OWA_FCTL