31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00
TX_DATA
Bits
31 :
0W
0x0
Transmitting left, right channel sample data should be written this register one
by one. The left channel sample data is first and then the right channel sample.