31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00
Unused
Bits
31 :
12
DAC_MODU_SELECT
Bit
11R/W
0x0
DAC Modulator Debug
0: DAC Modulator Normal Mode
1: DAC Modulator Debug Mode
DAC_PATTERN_SELECT
Bits
10 :
9R/W
0x0
DAC Pattern Select
00: Normal (Audio Sample from TX FIFO)
01: -6 dB Sin wave
10: -60 dB Sin wave
11: Silent wave
CODEC_CLK_SELECT
Bit
8R/W
0x0
CODEC Clock Source Select
0: CODEC Clock from PLL
1: CODEC Clock from OSC (for Debug)
Unused
Bit
7
DA_SWP
Bit
6R/W
0x0
DAC Output Channel Swap Enable
0:Disable
1:Enable
Unused
Bits
5 :
2
ADDA_LOOP_MODE
Bits
1 :
0R/W
0x0
ADDA Loop Mode Select
00: Disable
01: ADDA LOOP MODE DACL/DACR connect to ADCL/ADCR
10: ADDA LOOP MODE DACL/DACR connect to ADCX/ADCY
11: Reserved