Регистры Allwinner H616
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IOMMU_DM_AUT_OVWT_REG
3.12.5. IOMMU Domain Authority Overwrite Register - адрес: 0x30f00d0 (смещение: 0x00D0)

Модуль управления памятью ввода-вывода IOMMU: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

  DM_AUT_OVWT_ENABLE

Bit 31
R/W
0x0

Domain write/read permission overwrite enable
0: Disable
1: Enable

  Unused

Bits 30 : 14

  M6_WT_AUT_OVWT_CTRL

Bit 13
R/W
0x0

Master6 write permission overwrite control
0: The write-operation is permitted
1: The write-operation is prohibited

  M6_RD_AUT_OVWT_CTRL

Bit 12
R/W
0x0

Master6 read permission overwrite control
0: The read-operation is permitted
1: The read-operation is prohibited

  M5_WT_AUT_OVWT_CTRL

Bit 11
R/W
0x0

Master5 write permission overwrite control
0: The write-operation is permitted
1: The write-operation is prohibited

  M5_RD_AUT_OVWT_CTRL

Bit 10
R/W
0x0

Master5 read permission overwrite control
0: The read-operation is permitted
1: The read-operation is prohibited

  M4_WT_AUT_OVWT_CTRL

Bit 9
R/W
0x0

Master5 write permission overwrite control
0: The write-operation is permitted
1: The write-operation is prohibited

  M4_RD_AUT_OVWT_CTRL

Bit 8
R/W
0x0

Master5 read permission overwrite control
0: The read-operation is permitted
1: The read-operation is prohibited

  M3_WT_AUT_OVWT_CTRL

Bit 7
R/W
0x0

Master3 write permission overwrite control
0: The write-operation is permitted
1: The write-operation is prohibited

  M3_RD_AUT_OVWT_CTRL

Bit 6
R/W
0x0

Master3 read permission overwrite control
0: The read-operation is permitted
1: The read-operation is prohibited

  M2_WT_AUT_OVWT_CTRL

Bit 5
R/W
0x0

Master2 write permission overwrite control
0: The write-operation is permitted
1: The write-operation is prohibited

  M2_RD_AUT_OVWT_CTRL

Bit 4
R/W
0x0

Master2 read permission overwrite control
0: The read-operation is permitted
1: The read-operation is prohibited

  M1_WT_AUT_OVWT_CTRL

Bit 3
R/W
0x0

Master1 write permission overwrite control
0: The write-operation is permitted
1: The write-operation is prohibited

  M1_RD_AUT_OVWT_CTRL

Bit 2
R/W
0x0

Master1 read permission overwrite control
0: The read-operation is permitted
1: The read-operation is prohibited

  M0_WT_AUT_OVWT_CTRL

Bit 1
R/W
0x0

Master0 write permission overwrite control
0: The write-operation is permitted
1: The write-operation is prohibited

  M0_RD_AUT_OVWT_CTRL

Bit 0
R/W
0x0

Master0 read permission overwrite control
0: The read-operation is permitted
1: The read-operation is prohibited

Note
Setting the REG_ARD_OVWT can mask the Domain control defined by IOMMU_DM_AUT_CTRL_REG0~7. All the property of Level2 are covered by the property defined in REG_ARD_OVWT. Allow read and write for all by default.

Команда U-Boot для чтения регистра

md 30f00d0 1

Bit fields structure 

typedef union  iommu_dm_aut_ovwt_reg
{
  struct
  {
   unsigned m0_rd_aut_ovwt_ctrl : 1;
   unsigned m0_wt_aut_ovwt_ctrl : 1;
   unsigned m1_rd_aut_ovwt_ctrl : 1;
   unsigned m1_wt_aut_ovwt_ctrl : 1;
   unsigned m2_rd_aut_ovwt_ctrl : 1;
   unsigned m2_wt_aut_ovwt_ctrl : 1;
   unsigned m3_rd_aut_ovwt_ctrl : 1;
   unsigned m3_wt_aut_ovwt_ctrl : 1;
   unsigned m4_rd_aut_ovwt_ctrl : 1;
   unsigned m4_wt_aut_ovwt_ctrl : 1;
   unsigned m5_rd_aut_ovwt_ctrl : 1;
   unsigned m5_wt_aut_ovwt_ctrl : 1;
   unsigned m6_rd_aut_ovwt_ctrl : 1;
   unsigned m6_wt_aut_ovwt_ctrl : 1;
   unsigned unused0 : 17;
   unsigned dm_aut_ovwt_enable : 1;
  } b;
   unsigned long w;
} IOMMU_DM_AUT_OVWT_REG
Allwinner H616 Manual