Регистры H616: IOMMU Interrupt Enable Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 18

L2_PAGE_TABLE_INVALID_EN

Bit 17
R/W
0x0

Level2 page table invalid interrupt enable
0: Mask interrupt
1: Enable interrupt

L1_PAGE_TABLE_INVALID_EN

Bit 16
R/W
0x0

Level1 page table invalid interrupt enable
0: Mask interrupt
1: Enable interrupt

Unused

Bits 15 : 7

MICRO_TLB6_INVALID_EN

Bit 6
R/W
0x0

Micro TLB6 permission invalid interrupt enable
0: Mask interrupt
1: Enable interrupt

MICRO_TLB5_INVALID_EN

Bit 5
R/W
0x0

Micro TLB5 permission invalid interrupt enable
0: Mask interrupt
1: Enable interrupt

MICRO_TLB4_INVALID_EN

Bit 4
R/W
0x0

Micro TLB4 permission invalid interrupt enable
0: Mask interrupt
1: Enable interrupt

MICRO_TLB3_INVALID_EN

Bit 3
R/W
0x0

Micro TLB3 permission invalid interrupt enable
0: Mask interrupt
1: Enable interrupt

MICRO_TLB2_INVALID_EN

Bit 2
R/W
0x0

Micro TLB2 permission invalid interrupt enable
0: Mask interrupt
1: Enable interrupt

MICRO_TLB1_INVALID_EN

Bit 1
R/W
0x0

Micro TLB1 permission invalid interrupt enable
0: Mask interrupt
1: Enable interrupt

MICRO_TLB0_INVALID_EN

Bit 0
R/W
0x0

Micro TLB0 permission invalid interrupt enable
0: Mask interrupt
1: Enable interrupt

Note
Invalid page table and permission error can not make one device or multi-devices in system work normally.
Permission error usually happens in MicroTLB. The error generates interrupt, and waits for processing through software.
Invalid page table usually happens in MacroTLB. The error can not influence the access of other devices. So the error page table needs go back the way it comes, but the error should not be written in each level TLB.

Bit fields structure

typedef union iommu_int_enable_reg { struct { unsigned micro_tlb0_invalid_en : 1; unsigned micro_tlb1_invalid_en : 1; unsigned micro_tlb2_invalid_en : 1; unsigned micro_tlb3_invalid_en : 1; unsigned micro_tlb4_invalid_en : 1; unsigned micro_tlb5_invalid_en : 1; unsigned micro_tlb6_invalid_en : 1; unsigned unused0 : 9; unsigned l1_page_table_invalid_en : 1; unsigned l2_page_table_invalid_en : 1; unsigned unused1 : 14; } b; unsigned long w; } IOMMU_INT_ENABLE_REG