Регистры H616: IOMMU Interrupt Clear Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 18

L2_PAGE_TABLE_INVALID_CLR

Bit 17
W
0x0

Level2 page table invalid interrupt clear bit
0: Invalid operation
1: Clear interrupt

L1_PAGE_TABLE_INVALID_CLR

Bit 16
W
0x0

Level1 page table invalid interrupt clear bit
0: Invalid operation
1: Clear interrupt

Unused

Bits 15 : 7

MICRO_TLB6_INVALID_CLR

Bit 6
W
0x0

Micro TLB6 permission invalid interrupt clear bit
0: Invalid operation
1: Clear interrupt

MICRO_TLB5_INVALID_CLR

Bit 5
W
0x0

Micro TLB5 permission invalid interrupt clear bit
0: Invalid operation
1: Clear interrupt

MICRO_TLB4_INVALID_CLR

Bit 4
W
0x0

Micro TLB4 permission invalid interrupt clear bit
0: Invalid operation
1: Clear interrupt

MICRO_TLB3_INVALID_CLR

Bit 3
W
0x0

Micro TLB3 permission invalid interrupt clear bit
0: Invalid operation
1: Clear interrupt

MICRO_TLB2_INVALID_CLR

Bit 2
W
0x0

Micro TLB2 permission invalid interrupt clear bit
0: Invalid operation
1: Clear interrupt

MICRO_TLB1_INVALID_CLR

Bit 1
W
0x0

Micro TLB1 permission invalid interrupt clear bit
0: Invalid operation
1: Clear interrupt

MICRO_TLB0_INVALID_CLR

Bit 0
W
0x0

Micro TLB0 permission invalid interrupt clear bit
0: Invalid operation
1: Clear interrupt

Bit fields structure

typedef union iommu_int_clr_reg { struct { unsigned micro_tlb0_invalid_clr : 1; unsigned micro_tlb1_invalid_clr : 1; unsigned micro_tlb2_invalid_clr : 1; unsigned micro_tlb3_invalid_clr : 1; unsigned micro_tlb4_invalid_clr : 1; unsigned micro_tlb5_invalid_clr : 1; unsigned micro_tlb6_invalid_clr : 1; unsigned unused0 : 9; unsigned l1_page_table_invalid_clr : 1; unsigned l2_page_table_invalid_clr : 1; unsigned unused1 : 14; } b; unsigned long w; } IOMMU_INT_CLR_REG