Регистры H616: TWI Clock Control Register

TWI_CCR

9.1.5. TWI Clock Control Register - адрес: 0x5002014 0x5002414 0x5002814 0x5002c14 0x5003014 0x7081414 (смещение: 0x0014)

Двухпроводной интерфейс: список регистров

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 8

CLK_DUTY

Bit 7
R/W
0x1

Setting duty cycle of Clock as Master
0: 50%
1: 40%

CLK_M

Bits 6 : 3
R/W
0x0

CLK_N

Bits 2 : 0
R/W
0x0

The TWI bus is sampled by the TWI at the frequency defined by F0:
Fsamp = F0 = Fin / 2^CLK_N
The TWI OSCL output frequency, in master mode, is F1 / 10:
F1 = F0 / (CLK_M + 1)
Foscl = F1 / 10 = Fin / (2^CLK_N * (CLK_M + 1)*10)
Specially, Foscl = F1/11 when CLK_M=0 and CLK_DUTY=40% due to the delay of SCL sample debounce.

For Example:
Fin = 24 MHz (APB clock input)
For 400 kHz full speed 2Wire, CLK_N = 1, CLK_M=2
F0 = 24 MHz/2^1=12 MHz, F1= F0/(10*(2+1)) = 0.4 MHz
For 100 kHz standard speed 2Wire, CLK_N=1, CLK_M=11
F0=24 MHz/2^1=12 MHz, F1=F0/(10*(11+1)) = 0.1 MHz

Bit fields structure

typedef union twi_ccr { struct { unsigned clk_n : 3; unsigned clk_m : 4; unsigned clk_duty : 1; unsigned unused0 : 24; } b; unsigned long w; } TWI_CCR