Двухпроводной интерфейс: список регистров

  START_TRAN

0: Transmission idle
1: Start transmission
Automatically cleared to '0' when finished. If slave not respond for the
expected status over the time defined by TIMEOUT, current transmission
will stop. All format setting and data will be loaded from registers and FIFO
when transmission start.

  Unused

  RESTART_MODE

0: RESTART
1: STOP+START
Define the TWI_DRV action after sending register address.

  READ_TRAN_MODE

0: send slave_id+W
1: do not send slave_id+W
Setting this bit to 1 if reading from a slave which register width is equal to 0

  TRAN_RESULT

000: OK
001: FAIL
Other: Reserved

  TWI_STA

0x00: bus error
0x08: START condition transmitted
0x10: Repeated START condition transmitted
0x18: Address + Write bit transmitted, ACK received
0x20: Address + Write bit transmitted, ACK not received
0x28: Data byte transmitted in master mode, ACK received
0x30: Data byte transmitted in master mode, ACK not received
0x38: Arbitration lost in address or data byte
0x40: Address + Read bit transmitted, ACK received
0x48: Address + Read bit transmitted, ACK not received
0x50: Data byte received in master mode, ACK received
0x58: Data byte received in master mode, ACK not received
0x01: Timeout when sending 9th SCL clk
Other: Reserved

  TIMEOUT_N

When sending the 9th clock, assert fail signal when slave device does not
response after N*FSCL cycles. And software must do a reset to TWI_DRV
module and send a stop condition to slave.

  Unused

  SOFT_RESET

0: normal
1: reset

  TWI_DRV_EN

0: Module disable
1: Module enable (only use in TWI Master Mode)

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  twi_drv_ctrl
{
  struct
  {
   unsigned twi_drv_en : 1;
   unsigned soft_reset : 1;
   unsigned unused0 : 6;
   unsigned timeout_n : 8;
   unsigned twi_sta : 8;
   unsigned tran_result : 4;
   unsigned read_tran_mode : 1;
   unsigned restart_mode : 1;
   unsigned unused1 : 1;
   unsigned start_tran : 1;
  } b;
   unsigned long w;
} TWI_DRV_CTRL