Регистры H616: TWI_DRV Bus Control Register

31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00

Unused

Bits 31 : 17

CLK_COUNT_MODE

Bit 16
W
0x0

0: scl clock high period count on oscl
1: scl clock high period count on iscl

CLK_DUTY

Bit 15
R/W
0x1

Setting duty cycle of Clock as Master
0: 50%
1: 40%

CLK_N

Bits 14 : 12
R/W
0x0

TWI_DRV bus sampling clock F0=24 MHz/2^CLK_N

CLK_M

Bits 11 : 8
R/W
0x0

TWI_DRV output SCL frequency is FSCL=F1/10=(F0/(CLK_M+1))/10
Specially,Foscl = F1/11 when CLK_M=0 and CLK_DUTY=40% due to the delay
of SCL sample debounce.

SCL_STA

Bit 7
R
0x1

SCL current status

SDA_STA

Bit 6
R
0x1

SDA current status

Unused

Bits 5 : 4

SCL_MOV

Bit 3
R/W
0x0

SCL manual output value

SDA_MOV

Bit 2
R/W
0x0

SDA manual output value

SCL_MOE

Bit 1
R/W
0x0

SCL manual output en

SDA_MOE

Bit 0
R/W
0x0

SDA manual output en

Bit fields structure

typedef union twi_drv_bus_ctrl { struct { unsigned sda_moe : 1; unsigned scl_moe : 1; unsigned sda_mov : 1; unsigned scl_mov : 1; unsigned unused0 : 2; unsigned sda_sta : 1; unsigned scl_sta : 1; unsigned clk_m : 4; unsigned clk_n : 3; unsigned clk_duty : 1; unsigned clk_count_mode : 1; unsigned unused1 : 15; } b; unsigned long w; } TWI_DRV_BUS_CTRL