Unused Bits 31 : 8
DLH Bits 7 : 0
R/W
0x0
Divisor Latch High
Upper 8 bits of a 16 bits, read/write, Divisor Latch Register contains the
baud rate divisor for the UART. This register may only be accessed when
the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero).
The output baud rate is equal to the serial clock (sclk) frequency divided by
sixteen times the value of the baud rate divisor, as follows: baud rate =
(serial clock freq) / (16 * divisor).
Note that when the Divisor Latch Registers (DLL and DLH) is set to zero, the
baud clock is disabled and no serial communications occur. Also, once the
DLH is set, at least 8 clock cycles of the slowest UART clock should be
allowed to pass before transmitting or receiving data.
Команда U-Boot для чтения регистра md 5000004 1 md 5000404 1 md 5000804 1 md 5000c04 1 md 5001004 1 md 5001404 1
Bit fields structure
typedef union uart_dlh
{
struct
{
unsigned dlh : 8;
unsigned unused0 : 24;
} b;
unsigned long w;
} UART_DLH
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