Универсальный асинхронный приемо-передатчик: список регистров

  Unused

  RCVR_TRIGGER

This is used to select the trigger level in the receiver FIFO when the
Received Data Available Interrupt is generated. In auto flow control mode it
is used to determine when the rts_n signal is de-asserted. It also
determines when the dma_rx_req_n signal is asserted in certain modes of
operation.
00: 1 character in the FIFO
01: FIFO 1/4 full
10: FIFO 1/2 full
11: FIFO-2 less than full

  TFT

TX Empty Trigger
This is used to select the empty threshold level when the THRE Interrupts
are generated and the mode is active. It also determines when the
dma_tx_req_n signal is asserted in certain modes of operation.
00: FIFO empty
01: 2 characters in the FIFO
10: FIFO 1/4 full
11: FIFO 1/2 full

  DMAM

DMA Mode
0: Mode 0
In this mode, if PTE is high and TX FIFO is enabled, the TX DMA request will
send when TFL is less than or equal to FIFO Trigger Level. If PTE is high and
TX FIFO is disabled, the TX DMA request will send when THRE is empty. If
PTE is low, the TX DMA request will send when the TX FIFO is empty.
If dma_pte_rx is high and RX FIFO is enabled, the rx drq will send when RFL
is equal to or more than FIFO Trigger Level.

1: Mode 1
In this mode, if TX FIFO is enabled and the PTE is high, the TX DMA request
will send when TFL is less than or equal to FIFO Trigger Level. If PTE is low,
the TX DMA request will send when TX FIFO is empty and the request stops
only when TX FIFO is full.
If RFL is equal to or more than FIFO Trigger Level, the rx drq will be set to 1,
in otherwise, it will be set to 0.

  XFIFOR

XMIT FIFO Reset
The bit resets the control portion of the transmit FIFO and treats the FIFO
as empty. This also de-asserts the DMA TX request.
It is 'self-clearing'. It is not necessary to clear this bit.

  RFIFOR

RCVR FIFO Reset
The bit resets the control portion of the receive FIFO and treats the FIFO as
empty. This also de-asserts the DMA RX request.
It is 'self-clearing'. It is not necessary to clear this bit.

  FIFOE

Enable FIFOs
The bit enables/disables the transmit (XMIT) and receive (RCVR) FIFOs.
Whenever the value of this bit is changed, both the XMIT and RCVR
controller portion of FIFOs is reset.

Команда U-Boot для чтения регистра

Bit fields structure

typedef union  uart_fcr
{
  struct
  {
   unsigned fifoe : 1;
   unsigned rfifor : 1;
   unsigned xfifor : 1;
   unsigned dmam : 1;
   unsigned tft : 2;
   unsigned rcvr_trigger : 2;
   unsigned unused0 : 24;
  } b;
   unsigned long w;
} UART_FCR