31 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 16
15 |•|•|•|•|•|•|•|•|•|•|•|•|•|•|•|•| 00
Unused
Bits
31 :
8
UART_FUNCTION
Bits
7 :
6R/W
0x0
Select IrDA or RS485
00:UART Mode
01:IrDA SIR Mode
10:RS485 Mode
11:Reserved
AFCE
Bit
5R/W
0x0
Auto Flow Control Enable
When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set,
Auto Flow Control features are enabled.
0: Auto Flow Control mode disabled
1: Auto Flow Control mode enabled
LOOP
Bit
4R/W
0x0
Loop Back Mode
0: Normal Mode
1: Loop Back Mode
This is used to put the UART into a diagnostic mode for test purposes. If
operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] is set
to zero), data on the sout line is held high, while serial data output is looped
back to the sin line, internally.
In this mode all the interrupts are fully functional.
Also, in loopback mode, the modem control inputs (dsr_n, cts_n,
ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n,
out1_n, out2_n) are looped back to the inputs, internally.
If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] is set to one),
data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line.
Unused
Bits
3 :
2
RTS
Bit
1R/W
0x0
Request to Send
This is used to directly control the Request to Send (rts_n) output. The RTS
(rts_n) output is used to inform the modem or data set that the UART is
ready to exchange data. When Auto RTS Flow Control is not enabled
(MCR[5] is set to zero), the rts_n signal is set low by programming MCR[1]
(RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active
(MCR[5] is set to one) and FIFOs enable (FCR[0] is set to one), the rts_n
output is controlled in the same way, but is also gated with the receiver FIFO
threshold trigger (rts_n is inactive high when above the threshold). The
rts_n signal is de-asserted when MCR[1] is set low.
0: rts_n de-asserted (logic 1)
1: rts_n asserted (logic 0)
Note that in Loopback mode (MCR[4] is set to one), the rts_n output is held
inactive high while the value of this location is internally looped back to an input.
DTR
Bit
0R/W
0x0
Data Terminal Ready
This is used to directly control the Data Terminal Ready (dtr_n) output. The
value written to this location is inverted and driven out on dtr_n.
0: dtr_n de-asserted (logic 1)
1: dtr_n asserted (logic 0)
The Data Terminal Ready output is used to inform the modem or data set
that the UART is ready to establish communications.
Note that in Loopback mode (MCR[4] is set to one), the dtr_n output is held
inactive high while the value of this location is internally looped back to an input.