Unused

  FIFOERR

RX Data Error in FIFO
When FIFOs are disabled, this bit is always 0. When FIFOs are enabled, this
bit is set to \"1\" when there is at least one PE, FE, or BI in the RX FIFO. It is
cleared by a read from the LSR register provided, there are no subsequent
errors in the FIFO.

  TEMT

Transmitter Empty
If the FIFOs are disabled, this bit is set to \"1\" whenever the TX Holding
Register and the TX Shift Register are empty. If the FIFOs are enabled, this
bit is set whenever the TX FIFO and the TX Shift Register are empty. In both
cases, this bit is cleared when a byte is written to the TX data channel.

  THRE

TX Holding Register Empty
If the FIFOs are disabled, this bit is set to \"1\" whenever the TX Holding
Register is empty and ready to accept new data and it is cleared when the
CPU writes to the TX Holding Register.
If the FIFOs are enabled, this bit is set to \"1\" whenever the TX FIFO is empty
and it is cleared when at least one byte is written to the TX FIFO.

  BREAK_INTERRUPT

This is used to indicate the detection of a break sequence on the serial input data.
If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input,
sir_in, is held in a logic '0' state for longer than the sum of start time + data
bits + parity + stop bits.
If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial
input, sir_in, is continuously pulsed to logic '0' for longer than the sum of
start time + data bits + parity + stop bits. A break condition on serial input
causes one and only one character, consisting of all zeros, to be received by the UART.
In the FIFO mode, the character associated with the break condition is
carried through the FIFO and is revealed when the character is at the top of
the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI
indication occurs immediately and persists until the LSR is read.

  FRAMING_ERROR

This is used to indicate the occurrence of a framing error in the receiver. A
framing error occurs when the receiver does not detect a valid STOP bit in
the received data.
In the FIFO mode, since the framing error is associated with a character
received, it is revealed when the character with the framing error is at the
top of the FIFO. When a framing error occurs, the UART tries to
resynchronize. It does this by assuming that the error was due to the start
bit of the next character and then continues receiving the other bit i.e. data,
and/or parity and stop. It should be noted that the Framing Error (FE) bit
(LSR[3]) is set if a break interrupt has occurred, as indicated by Break
Interrupt (BI) bit (LSR[4]).
0: no framing error
1:framing error
Reading the LSR clears the FE bit.

  PARITY_ERROR

This is used to indicate the occurrence of a parity error in the receiver if the
Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity
error is associated with a character received, it is revealed when the
character with the parity error arrives at the top of the FIFO. It should be
noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has
occurred, as indicated by Break Interrupt (BI) bit (LSR[4]).
0: no parity error
1: parity error
Reading the LSR clears the PE bit.

  OVERRUN_ERROR

This occurs if a new data character was received before the previous data
was read. In the non-FIFO mode, the OE bit is set when a new character
arrives in the receiver before the previous character was read from the RBR.
When this happens, the data in the RBR is overwritten. In the FIFO mode, an
overrun error occurs when the FIFO is full and a new character arrives at the
receiver. The data in the FIFO is retained and the data in the receive shift
register is lost.
0: no overrun error
1: overrun error
Reading the LSR clears the OE bit.

  DATA_READY

This is used to indicate that the receiver contains at least one character in
the RBR or the receiver FIFO.
0: no data ready
1: data ready
This bit is cleared when the RBR is read in non-FIFO mode, or when the
receiver FIFO is empty, in FIFO mode.

typedef union  uart_lsr
{
  struct
  {
   unsigned data_ready : 1;
   unsigned overrun_error : 1;
   unsigned parity_error : 1;
   unsigned framing_error : 1;
   unsigned break_interrupt : 1;
   unsigned thre : 1;
   unsigned temt : 1;
   unsigned fifoerr : 1;
   unsigned unused0 : 24;
  } b;
   unsigned long w;
} UART_LSR