Unused Bits 31 : 8
DCD Bit 7
R
0x0
Line State of Data Carrier Detect
This is used to indicate the current state of the modem control line dcd_n.
This bit is the complement of dcd_n.
When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set.
0: dcd_n input is de-asserted (logic 1)
1: dcd_n input is asserted (logic 0)
RING_INDICATOR Bit 6
R
0x0
Line State of Ring Indicator (RI)
This is used to indicate the current state of the modem control line ri_n.
This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is
asserted it is an indication that a telephone ringing signal has been received
by the modem or data set.
0: ri_n input is de-asserted (logic 1)
1: ri_n input is asserted (logic 0)
DSR Bit 5
R
0x0
Line State of Data Set Ready
This is used to indicate the current state of the modem control line dsr_n.
This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n)
is asserted it is an indication that the modem or data set is ready to
establish communications with UART.
0: dsr_n input is de-asserted (logic 1)
1: dsr_n input is asserted (logic 0)
In Loopback Mode (MCR[4] is set to 1), DSR is the same as MCR[0] (DTR).
CTS Bit 4
R
0x0
Line State of Clear To Send
This is used to indicate the current state of the modem control line cts_n.
This bit is the complement of cts_n. When the Clear to Send input (cts_n) is
asserted it is an indication that the modem or data set is ready to exchange
data with UART.
0: cts_n input is de-asserted (logic 1)
1: cts_n input is asserted (logic 0)
In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS).
DDCD Bit 3
RC
0x0
Delta Data Carrier Detect
This is used to indicate that the modem control line dcd_n has changed
since the last time the MSR was read.
0: no change on dcd_n since last read of MSR
1: change on dcd_n since last read of MSR
Reading the MSR clears the DDCD bit.
Note: If the DDCD bit is not set and the dcd_n signal is asserted (low) and
a reset occurs (software or otherwise), then the DDCD bit is set when the
reset is removed if the dcd_n signal remains asserted.
TERI Bit 2
RC
0x0
Trailing Edge Ring Indicator
This is used to indicate that a change on the input ri_n (from an active-low
to an inactive-high state) has occurred since the last time the MSR was read.
0: no change on ri_n since last read of MSR
1: change on ri_n since last read of MSR
Reading the MSR clears the TERI bit.
DDSR Bit 1
RC
0x0
Delta Data Set Ready
This is used to indicate that the modem control line dsr_n has changed since
the last time the MSR was read.
0: no change on dsr_n since last read of MSR
1: change on dsr_n since last read of MSR
Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR
reflects changes on MCR[0] (DTR).
Note: If the DDSR bit is not set and the dsr_n signal is asserted (low) and a
reset occurs (software or otherwise), then the DDSR bit is set when the
reset is removed if the dsr_n signal remains asserted.
DCTS Bit 0
RC
0x0
Delta Clear to Send
This is used to indicate that the modem control line cts_n has changed since
the last time the MSR was read.
0: no change on ctsdsr_n since last read of MSR
1: change on ctsdsr_n since last read of MSR
Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS
reflects changes on MCR[1] (RTS).
Note: If the DCTS bit is not set and the cts_n signal is asserted (low) and a
reset occurs (software or otherwise), then the DCTS bit is set when the
reset is removed if the cts_n signal remains asserted.
Команда U-Boot для чтения регистра md 5000018 1 md 5000418 1 md 5000818 1 md 5000c18 1 md 5001018 1 md 5001418 1
Bit fields structure
typedef union uart_msr
{
struct
{
unsigned dcts : 1;
unsigned ddsr : 1;
unsigned teri : 1;
unsigned ddcd : 1;
unsigned cts : 1;
unsigned dsr : 1;
unsigned ring_indicator : 1;
unsigned dcd : 1;
unsigned unused0 : 24;
} b;
unsigned long w;
} UART_MSR
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