Регистры Allwinner H616

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UART_USR
9.2.5. UART Status Register - адрес: 0x500007c 0x500047c 0x500087c 0x5000c7c 0x500107c 0x500147c (смещение: 0x007C)

Универсальный асинхронный приемо-передатчик: список регистров



31 ||||||||||||||||| 16
15 ||||||||||||||||| 00

  Unused

Bits 31 : 5

  RFF

Bit 4
R
0x0

Receive FIFO Full
This is used to indicate that the receive FIFO is completely full.
0: Receive FIFO not full
1: Receive FIFO Full
This bit is cleared when the RX FIFO is no longer full.


  RFNE

Bit 3
R
0x0

Receive FIFO Not Empty
This is used to indicate that the receive FIFO contains one or more entries.
0: Receive FIFO is empty
1: Receive FIFO is not empty
This bit is cleared when the RX FIFO is empty.


  TFE

Bit 2
R
0x1

Transmit FIFO Empty
This is used to indicate that the transmit FIFO is completely empty.
0: Transmit FIFO is not empty
1: Transmit FIFO is empty
This bit is cleared when the TX FIFO is no longer empty.


  TFNF

Bit 1
R
0x1

Transmit FIFO Not Full
This is used to indicate that the transmit FIFO in not full.
0: Transmit FIFO is full
1: Transmit FIFO is not full
This bit is cleared when the TX FIFO is full.


  BUSY

Bit 0
R
0x0

UART Busy Bit
0: Idle or inactive
1: Busy



Команда U-Boot для чтения регистра

md 500007c 1
md 500047c 1
md 500087c 1
md 5000c7c 1
md 500107c 1
md 500147c 1



Bit fields structure

typedef union  uart_usr
{
  struct
  {
   unsigned busy : 1;
   unsigned tfnf : 1;
   unsigned tfe : 1;
   unsigned rfne : 1;
   unsigned rff : 1;
   unsigned unused0 : 27;
  } b;
   unsigned long w;
} UART_USR
   

Allwinner H616 Manual